ST10F269ZX datasheet(19/184 Pages) STMICROELECTRONICS

19 / 184 page

ST10F269

5 - INTERNAL FLASH MEMORY

19/184

temporarily

unlocked

for

update

(write)

operations.

With the two possibilities for write protection -

whole memory or block specific - a flexible

installation of write protection is supported to

protect the Flash memory or parts of it from

unauthorized programming or erase accesses

and to provide virus-proof protection for all system

code blocks. All write protection also is enabled

during boot operation.

Power Supply, Reset

The Flash module uses a single power supply for

both

read

and

write

functions.

Internally

generated and regulated voltages are provided for

the program and erase operations from 5V supply.

Once a program or erase cycle has been

completed, the device resets to the standard read

mode. At power-on, the Flash memory has a

setup phase of some microseconds (dependent

on the power supply ramp-up). During this phase,

Flash can not be read. Thus, if EA pin is high

(execution will start from Flash memory), the CPU

will remains in reset state until the Flash can be

accessed.

5.3 - Architectural Description

The

Flash

module

distinguishes

two

basic

operating modes, the standard read mode and the

command mode. The initial state after power-on

and after reset is the standard read mode.

5.3.1 - Read Mode

The Flash module enters the standard operating

mode, the read mode:

– After Reset command

– After every completed erase operation

– After every completed programming operation

– After

every

other

completed

command

execution

– Few microseconds after a CPU-reset has

started

– After incorrect address and data values of

command sequences or writing them in an

improper sequence

– After incorrect write access to a read protected

Flash memory

The read mode remains active until the last

command of a command sequence is decoded

which starts directly a Flash array operation, such

as:

– erase one or several blocks

– program a word into Flash array

– protect / temporary unprotect a block.

In the standard read mode read accesses are

directly controlled by the Flash memory array,

delivering

32-bit

double

Word

from

the

addressed position. Read accesses are always

aligned to double Word boundaries. Thus, both

low order address bit A1 and A0 are not used in

the Flash array for read accesses. The high order

address bit A17/A16 define the physical 64K Byte

segment being accessed within the Flash array.

5.3.2 - Command Mode

Every operation besides standard read operations

is initiated by commands written to the Flash

command register. The addresses used for

command cycles define in conjunction with the

actual state the specific step within command

sequences. With the last command of a command

sequence, the Erase-Program Controller (EPC)

starts the execution of the command. The EPC

status is indicated during command execution by:

– The Status Register,

– The Ready/Busy signal.

5.3.3 - Ready/Busy Signal

The Ready/Busy (R/B) signal is connected to the

XPER2 interrupt node (XP2IC). When R/B is high,

the Flash is busy with a Program or Erase

operation and will not accept any additional

program or erase instruction. When R/B is Low,

the Flash is ready for any Read/Write or Erase

operation. The R/B will also be low when the

memory is put in Erase Suspend mode.

This signal can be polled by reading XP2IC

when the Flash goes from Busy to Ready.

5.3.4 - Flash Status Register

The Flash Status register is used to flag the status

of the Flash memory and the result of an

operation. This register can be accessed by Read

cycles

during

the

program-Erase

Controller

operations. The program or erase operation can

be controlled by data polling on bit FSB.7 of

Status Register, detection of Toggle on FSB.6 and

FSB.2, or Error on FSB.5 and Erase Time-out on

FSB.3 bit. Any read attempt in Flash during EPC

operation will automatically output these five bits.

The EPC sets bit FSB.2, FSB.3, FSB.5, FSB.6

and FSB.7. Other bits are reserved for future use

and should be masked.

ST10F269ZX 数据表(PDF) 19 Page - STMicroelectronics

ST10F269ZX 数据表(HTML) 19 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载