ST10F269ZX datasheet(175/184 Pages) STMICROELECTRONICS

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ST10F269

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Note: 1. Timing guaranteed by design.

The formula for SSC Clock Cycle time is : t300 = 4 TCL * (<SSCBR> + 1)

Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer

Notes: 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge

(drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO =

0b).

2. The bit timing is repeated for all bits to be transmitted or received.

21.4.14.2 Slave mode

VCC = 5V ±10%, VSS = 0V, CPU clock = 40MHz, TA = -40 to +125°C, CL = 50pF (PQFP144 devices)

t318 SR Read data hold time after latch edge,

phase error detection off (SSCPEN = 0)

41.25

–

2TCL + 10

–

t318

Symbol

Parameter

Maximum Baud rate=6.25MBd

(<SSCBR> = 0001h)

Variable Baud rate

(<SSCBR>=0001h-FFFFh) Symb

Minimum

Maximum

Minimum

Maximum

Figure 82 : SSC Master Timing

303

304

305

306

1st Out Bit

Last Out Bit

2nd Out Bit

300

302

301

307

2nd.In Bit

1st.In Bit

308

307

Last.In Bit

308

SCLK

MTSR

MRST

Symbol

Parameter

Maximum Baud rate=10MBd

(<SSCBR> = 0001h)

Variable Baud rate

(<SSCBR>=0001h-FFFFh)

Unit

Minimum

Maximum

Minimum

Maximum

t310 SR SSC clock cycle time

100

8 TCL

262144 TCL

t311 SR SSC clock high time

–

t310/2 - 10

–ns

t312 SR SSC clock low time

–

t310/2 - 10

–ns

t313 SR SSC clock rise time

–

t314 SR SSC clock fall time

–

t315 CC Write data valid after shift edge

–

2 TCL + 14

t316 CC Write data hold after shift edge

–

t317p SR Read data setup time before latch

edge,

phase

error

detection

(SSCPEN = 1)

–

4TCL + 12

–

t318p

SR Read data hold time after latch edge,

phase

error

detection

(SSCPEN = 1)

–

6TCL + 12

–

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