AD7767

Rev. 0 | Page 18 of 24

DAISY CHAINING

Daisy chaining devices allows numerous devices to use the same

digital interface lines by cascading the outputs of multiple ADCs

on a single data line. This feature is especially useful for reduc-

ing component count and wiring connections, for example, in

isolated multiconverter applications or for systems with a limited

interfacing capacity. Data readback is analogous to clocking a

shift register where data is clocked on the falling edge of SCLK.

The block diagram in Figure 36 shows the way in which devices

must be connected in order to achieve daisy chain functionality.

This scheme operates by passing the output data of the SDO pin

of an AD7767 device to the SDI input of the next AD7767 device

in the chain. The data then continues through the chain until it

is clocked onto the SDO pin of the first device on the chain.

READING DATA IN DAISY CHAIN MODE

An example of a daisy chain of four AD7767 devices is shown in

Figure 36 and Figure 37. In the case illustrated in Figure 36, the

output of AD7767 (A) is the output of the full daisy chain. The

last device in the chain (AD7767 (D)) has its serial data in (SDI)

pin connected to ground. All the devices in the chain must use

common MCLK, SCLK, CS, and SYNC/PD signals.

To enable the daisy chain conversion process, apply a common

SYNC/PD pulse to all devices, synchronizing all the devices in

the chain (see the Power-Down, Reset, and Synchronization

section).

After applying a SYNC/PD pulse to all the devices, there is a

delay (as listed in Table 7) before valid conversion data appears

at the output of the chain of devices. As shown in Figure 37,

the first conversion result is output from the device labeled

AD7767 (A). This 24-bit conversion result is followed by the

conversion results from the devices B, C, and D, respectively,

with all conversion results output in an MSB first sequence. The

stream of conversion results is clocked through each device in

the chain and is eventually clocked onto the SDO pin of the

AD7767 (A) device. The conversion results of the all the devices

in the chain must be clocked onto the SDO pin of the final

device in the chain while its DRDY signal is active low. This is

illustrated in the example shown where the conversion results

from devices A, B, C, and D are clocked onto SDO (A) in the

time between the falling edge of DRDY (A) and the rising edge

of DRDY (A).

CHOOSING THE SCLK FREQUENCY

As shown in Figure 36, the number of SCLK falling edges that

occur during the period when DRDY (A) is active low must

match the number of devices in the chain multiplied by 24 (the

number of bits that must be clocked through onto SDO (A) for

each device).

length using a known common MCLK frequency must

therefore be established in advance. Note that the maximum

In the case where CS is tied logic low,

⎥⎦

⎤

⎢⎣

⎡

×

≤

K

t

t

READ

SCLK

24

(1)

where:

K is the number of AD7767 devices in the chain.

t

In the case where CS is used in the daisy chain interface,

(

) (

)

⎥⎦

⎤

⎢⎣

⎡

×

+

+

−

≤

K

t

t

t

t

t

13

7

6

READ

SCLK

24

(2)

where:

K is the number of AD7767 devices in the chain.

voltages.