PCA9665D datasheet(45/91 Pages) PHILIPS

45 / 91 page

PCA9665_2

Product data sheet

Rev. 02 — 7 December 2006

45 of 91

NXP Semiconductors

PCA9665

Fm+ parallel bus to I2C-bus controller

8.4.4 Slave Transmitter Buffered mode

In the Slave Transmitter Buffered mode, a number of data bytes are transmitted to a

master receiver several bytes at a time (see Figure 14). Data transfer is initialized as in the

Slave Receiver Buffered mode. When I2CADR and I2CCON have been initialized, the

PCA9665 waits until it is addressed by its own slave address followed by the data direction

bit which must be ‘1’ (R) for the PCA9665 to operate in the Slave Transmitter mode. After

its own slave address and the R bit have been received, the Serial Interrupt ﬂag (SI) is set,

the Interrupt line (INT) goes LOW and I2CSTA is loaded with A8h. This status code is

used to vector to an interrupt service routine, and the appropriate action to be taken is

detailed in Table 41.

The Slave Transmitter Buffered mode may also be entered if arbitration is lost while the

PCA9665 is in the master mode. See state B0h and appropriate actions in Table 41.

The byte count register (I2CCOUNT) is programmed with the number of bytes that need

to be sent in a single sequence (BC[6:0]) as shown in Table 39. LB bit is only used for the

Receiver Buffered modes and can be programmed to either logic 0 or logic 1.

If the AA bit is reset during a transfer, the PCA9665 will transmit all the bytes of the

transfer (values deﬁned by BC[6:0]) and enter state C8h. The PCA9665 is switched to the

not addressed slave mode and will ignore the master receiver if it continues the transfer.

Thus the master receiver receives all ‘1’s as serial data. While AA is reset, the PCA9665

does not respond to its own slave address. However, the I2C-bus is still monitored, and

address recognition may be resumed at any time by setting AA. This means that the AA

bit may be used to temporarily isolate the PCA9665 from the I2C-bus.

(1) See Table 31.

(2) Deﬁned state when the number of bytes sent is equal to the value in I2CCOUNT register.

(3) Deﬁned state when a NACK is received. The number of bytes transmitted is lower than or equal to the value in the

I2CCOUNT register.

(4) Deﬁned state after the last byte has been transmitted and the PCA9665 goes to the non-addressed mode (AA = 0) and an

ACK is received. The number of bytes that are transmitted is equal to the value in I2CCOUNT register.

Fig 14. Format and states in the Slave Transmitter Buffered mode (MODE = 1)

SLA

DATA

P or S

B8h

F8h

002aab662

reception of own

slave address and

transmission of one

or more data bytes

arbitration lost as MST and

addressed as slave

This number (contained in I2CSTA) corresponds

to a defined state of the I2C-bus.(1)

DATA

any number of data bytes and

their associated Acknowledge bits

from master to slave

from slave to master

DATA

C0h

P or S

F8h

C8h

on STOP

B0h

last data byte transmitted;

switched to Not Addressed slave

(AA bit in I2CCON = 0)

ALL '1's

(2)

(3)

(4)

A8h

PCA9665D 数据表(PDF) 45 Page - NXP Semiconductors

PCA9665D 数据表(HTML) 45 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

数据表下载

链接网址

PCA9665D 数据表(PDF) 45 Page - NXP Semiconductors

PCA9665D 数据表(HTML) 45 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

数据表 下载

链接网址

数据表下载