PCA9665PW datasheet(13/91 Pages) PHILIPS

13 / 91 page

PCA9665_2

Product data sheet

Rev. 02 — 7 December 2006

13 of 91

NXP Semiconductors

PCA9665

Fm+ parallel bus to I2C-bus controller

7.3.2.3

The Clock Rate registers, I2CSCLL and I2CSCLH (indirect addresses 02h and 03h)

I2CSCLL and I2CSCLH are 8-bit read/write registers. They deﬁne the data rate for the

PCA9665 when used as a bus master. The actual frequency is determined by tHIGH (time

where SCL is HIGH), tLOW (time where SCL is LOW), tr (rise time), and tf (fall time) values.

tHIGH and tLOW are calculated based on the values that are programmed into I2CSCLH

and I2CSCLL registers and the internal oscillator frequency. tr and tf are

system/application dependent.

with Tosc = internal oscillator period = 35 ns ± 5ns

Remark: The I2CMODE register needs to be programmed before programming the

I2CSCLL and I2CSCLH registers in order to know which I2C-bus mode is selected. See

Section 7.3.2.6 “The I2C-bus mode register, I2CMODE (indirect address 06h)” for more

detail.

Standard-mode is the default selected mode at power-up or after reset.

Table 17.

I2CSCLL - Clock Rate Low register (indirect address 02h) bit allocation

Table 18.

I2CSCLL - Clock Rate Low register (indirect address 02h) bit description

Bit

Symbol

Description

7:0

L[7:0]

Eight bits deﬁning the LOW state of SCL.

Table 19.

I2CSCLH - Clock Rate High register (indirect address 03h) bit allocation

Table 20.

I2CSCLH - Clock Rate High register (indirect address 03h) bit description

Bit

Symbol

Description

7:0

H[7:0]

Eight bits deﬁning the HIGH state of SCL.

SCL

osc I 2CSCLL

I 2CSCLH

() t

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