C8051F360 datasheet(5/288 Pages) SILABS

5 / 288 page

Rev. 1.0

C8051F360/1/2/3/4/5/6/7/8/9

13.3.2.16.4.2 PSWE Maintenance .................................................................... 141

13.3.3.System Clock ......................................................................................... 141

13.4.Flash Read Timing ......................................................................................... 143

14. Branch Target Cache ........................................................................................... 145

14.1.Cache and Prefetch Operation ....................................................................... 145

14.2.Cache and Prefetch Optimization................................................................... 146

15. External Data Memory Interface and On-Chip XRAM........................................ 153

15.1.Accessing XRAM............................................................................................ 153

15.1.1.16-Bit MOVX Example ........................................................................... 153

15.1.2.8-Bit MOVX Example ............................................................................. 153

15.2.Configuring the External Memory Interface .................................................... 154

15.3.Port Configuration........................................................................................... 154

15.4.Multiplexed and Non-multiplexed Selection.................................................... 157

15.4.1.Multiplexed Configuration....................................................................... 157

15.4.2.Non-multiplexed Configuration............................................................... 158

15.5.Memory Mode Selection................................................................................. 159

15.5.1.Internal XRAM Only ............................................................................... 159

15.5.2.Split Mode without Bank Select.............................................................. 159

15.5.3.Split Mode with Bank Select................................................................... 160

15.5.4.External Only.......................................................................................... 160

15.6.Timing .......................................................................................................... 160

15.6.1.Non-multiplexed Mode ........................................................................... 162

15.6.2.Multiplexed Mode ................................................................................... 165

16. Oscillators ............................................................................................................. 169

16.1.Programmable Internal High-Frequency (H-F) Oscillator ............................... 169

16.1.1. Internal Oscillator Suspend Mode ......................................................... 170

16.2.Programmable Internal Low-Frequency (L-F) Oscillator ................................ 171

16.2.1.Calibrating the Internal L-F Oscillator..................................................... 172

16.3.External Oscillator Drive Circuit...................................................................... 173

16.4.System Clock Selection.................................................................................. 173

16.5.External Crystal Example ............................................................................... 176

16.6.External RC Example ..................................................................................... 177

16.7.External Capacitor Example ........................................................................... 177

16.8.Phase-Locked Loop (PLL).............................................................................. 178

16.8.1.PLL Input Clock and Pre-divider ............................................................ 178

16.8.2.PLL Multiplication and Output Clock ...................................................... 178

16.8.3.Powering on and Initializing the PLL ...................................................... 179

17. Port Input/Output.................................................................................................. 183

17.1.Priority Crossbar Decoder .............................................................................. 185

17.2.Port I/O Initialization ....................................................................................... 187

17.3.General Purpose Port I/O ............................................................................... 190

18. SMBus ................................................................................................................... 202

18.1.Supporting Documents ................................................................................... 203

18.2.SMBus Configuration...................................................................................... 203

C8051F360 数据表(PDF) 5 Page - Silicon Laboratories

C8051F360 数据表(HTML) 5 Page - Silicon Laboratories

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载