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CS42L51 数据表(PDF) 21 Page - Cirrus Logic |
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CS42L51 数据表(HTML) 21 Page - Cirrus Logic |
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21 / 88 page  DS679F1 21 CS42L51 14. After powering up the CS42L51, RESET should be held low after the power supplies and clocks are settled. 15. See “Example System Clock Frequencies” on page 79 for typical MCLK frequencies. 16. See 17. “Master” on page 39 18. “MCLK” refers to the external master clock applied. Master Mode (Note 17) Output Sample Rate (LRCK) All Speed Modes (Note 17) Fs -Hz LRCK Duty Cycle 45 55 % SCLK Frequency 1/tP - 64•Fs Hz SCLK Duty Cycle 45 55 % LRCK Edge to SDOUT MSB Output Delay td(MSB) -52 ns SDOUT Setup Time Before SCLK Rising Edge ts(SDO-SK) 20 - ns SDOUT Hold Time After SCLK Rising Edge th(SK-SDO) 30 - ns SDIN Setup Time Before SCLK Rising Edge ts(SD-SK) 20 - ns SDIN Hold Time After SCLK Rising Edge th 20 - ns Parameters Symbol Min Max Units MCLK 128 ----------------- th(SK-SDO) // // // // // // // // ts(SD-SK) MSB MSB MSB-1 MSB-1 LRCK SCLK SDOUT SDIN td(MSB) ts(LK-SK) tP th ts(SDO-SK) Figure 4. Serial Audio Interface Slave Mode Timing th(SK-SDO) // // // // // // // // ts(SD-SK) MSB MSB MSB-1 MSB-1 LRCK SCLK SDOUT SDIN td(MSB) tP th ts(SDO-SK) Figure 5. Serial Audio Interface Master Mode Timing |
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