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DCS-7130-48LS-R 数据表(PDF) 3 Page - Arista Networks, Inc

部件名 DCS-7130-48LS-R
功能描述  7130LS Series Layer 1 FPGA Switch
PDF  8 Pages
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制造商  ARISTA [Arista Networks, Inc]
网页  https://www.arista.com/en/
标志 ARISTA - Arista Networks, Inc

DCS-7130-48LS-R 数据表(HTML) 3 Page - Arista Networks, Inc

  DCS-7130-48LS-R Datasheet HTML 1Page - Arista Networks, Inc DCS-7130-48LS-R Datasheet HTML 2Page - Arista Networks, Inc DCS-7130-48LS-R Datasheet HTML 3Page - Arista Networks, Inc DCS-7130-48LS-R Datasheet HTML 4Page - Arista Networks, Inc DCS-7130-48LS-R Datasheet HTML 5Page - Arista Networks, Inc DCS-7130-48LS-R Datasheet HTML 6Page - Arista Networks, Inc DCS-7130-48LS-R Datasheet HTML 7Page - Arista Networks, Inc DCS-7130-48LS-R Datasheet HTML 8Page - Arista Networks, Inc  
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7130LS Series | Applications
Enabling Custom Applications
While FPGA applications can be challenging to develop, the Arista 7130LS makes them easy to deploy. Arista provides a built-in
application framework allowing developers to wrap applications into simple packages for deployment, streamlining operational
processes. Arista development toolkits enable complete and unfettered access to the facilities provided by the in-system FPGAs.
These are the same APIs and developer kits used by the Arista engineering team to develop and deploy our applications.
Application
Dev
Standard Overview Key Features
Use it for...
ExchangeApp
L/LB
In-line
packet
time-
stamping
enabling
exchange
fairness
• Timestamp at the edge of trading
venue networks
• Sub-200ns passthrough latency to
apply the timestamp
• Reliable accuracy and timestamp
precision
• Accurately synchronise timestamps
between multiple ExchangeApp
devices
• Increase exchange fairness
• Reduce trading venue latency sensitivity
• Maintain trade order based on edge
timestamps
• Reduce complexity and risk of traditional
low-
latency exchange infrastructures
MetaProtect
Firewall
L/LB
Low-latency
packet
ltering in
135 ns
• Architected for ultra-low-latency
with forwarding from 135
nanoseconds
• Line rate 10GbE packet uni or
bidirectional ltering between port-
pairs
• Stateless security policy with up to
510 rules per ACL
• Full packet header logging for
noncompliant tra c
• Low-latency rewall
• Satisfy InfoSec or regulatory compliance
mandates without introducing excessive
latency



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