AD8307

Data Sheet

Rev. F | Page 14 of 24

INTERFACES

The AD8307 comprises six main amplifier/limiter stages, each

having a gain of 14.3 dB and small signal bandwidth of 900 MHz;

the overall gain is 86 dB with a −3 dB bandwidth of 500 MHz.

These six cells and their associated gm styled full-wave detectors

handle the lower two-thirds of the dynamic range. Three top-

end detectors, placed at 14.3 dB taps on a passive attenuator,

handle the upper third of the 90 dB range. Biasing for these cells

is provided by two references: one determines their gain and the

other is a band gap circuit that determines the logarithmic slope

and stabilizes it against supply and temperature variations. The

AD8307 can be enabled or disabled by a CMOS-compatible level

at ENB (Pin 6). The first amplifier stage provides a low voltage

noise spectral density (1.5 nV/√Hz).

The differential current-mode outputs of the nine detectors are

summed and then converted to single-sided form in the output

stage, nominally scaled 2 μA/dB. The logarithmic output voltage is

developed by applying this current to an on-chip 12.5 kΩ

resistor, resulting in a logarithmic slope of 25 mV/dB (that is,

500 mV/decade) at the OUT pin. This voltage is not buffered,

allowing the use of a variety of special output interfaces,

including the addition of postdemodulation filtering. The last

detector stage includes a modification to temperature stabilize the

log intercept, which is accurately positioned to make optimal

use of the full output voltage range available. The intercept can

be adjusted using the INT pin, which adds or subtracts a small

current to the signal current.

BAND GAP REFERENCE

AND BIASING

SIX 14.3dB 900MHz

AMPLIFIER STAGES

MIRROR

INPUT-OFFSET

COMPENSATION LOOP

COM

INM

INP

ENB

VPS

INT

OUT

OFS

AD8307

7.5mA

1.1kΩ

3

2

2µA

/dB

12.5kΩ

COM

NINE DETECTOR CELLS

SPACED 14.3dB

–INP

+INP

8

1

2

7

5

6

4

3

Figure 27. Main Features of the AD8307

The last gain stage also includes an offset sensing cell. This

generates a bipolarity output current when the main signal path

has an imbalance due to accumulated dc offsets. This current is

integrated by an on-chip capacitor, which can be increased in

value by an off-chip component at OFS. The resulting voltage is

used to null the offset at the output of the first stage. Because it

does not involve the signal input connections, whose ac-coupling

capacitors otherwise introduce a second pole in the feedback

path, the stability of the offset correction loop is assured.

The AD8307 is built on an advanced, dielectrically isolated,

complementary bipolar process. Most resistors are thin film

types having a low temperature coefficient of resistance (TCR)

and high linearity under large signal conditions. Their absolute

tolerance is typically within ±20%. Similarly, the capacitors have

a typical tolerance of ±15% and essentially zero temperature or

voltage sensitivity. Most interfaces have additional small junction

capacitances associated with them due to active devices or ESD

protection; these can be neither accurate nor stable. Component

numbering in each of these interface diagrams is local.

ENABLE INTERFACE

The chip enable interface is shown in Figure 28. The currents in

the diode-connected transistors control the turn-on and turn-

off states of the band gap reference and the bias generator, and

are a maximum of 100 μA when Pin 6 is taken to 5 V, under

worst-case conditions. Left unconnected, or at a voltage below

1 V, the AD8307 is disabled and consumes a sleep current of

under 50 μA; tied to the supply, or at a voltage above 2 V, it is

fully enabled. The internal bias circuitry is very fast, typically

<100 ns for either off or on. In practice, the latency period

before the log amp exhibits its full dynamic range is more likely

to be limited by factors relating to the use of ac coupling at the

input or the settling of the offset control loop.

COM

ENB

40kΩ

TO BIAS

STAGES

AD8307

6

2

Figure 28. Enable Interface

TOP-END

DETECTORS

COM

INP

INM

CD

CP

CM

COM

4kΩ

~3kΩ

125Ω

125Ω

6kΩ

6kΩ

2kΩ

2kΩ

TYP 2.2V FOR

3V SUPPLY,

3.2V AT 5V

S

S

VPS

COM

IE

2.4mA

Q1

Q2

2

7

8

1

Figure 29. Signal Input Interface

INPUT INTERFACE

Figure 29 shows the essentials of the signal input interface. CP

and CM are the parasitic capacitances to ground; CD is the

differential input capacitance, mostly due to Q1 and Q2. In

most applications, both input pins are ac-coupled. The switches

close when ENB is asserted. When disabled, the inputs float,

bias current IE is shut off, and the coupling capacitors remain

charged. If the log amp is disabled for long periods, small leakage

currents discharge these capacitors. If they are poorly matched,

charging currents at power-up can generate a transient input