AD8311

Rev. A | Page 13 of 24

Equation 6 can be restated as

First, the summed detector currents are written as a function of

the input power.

INT

IN

SLP

DET

I

P

I

I

+

×

=

(3)

()

sT

V

P

V

V

s

V

INT

IN

SLP

SET

APC

−

×

−

=

(7)

where:

where:

VSLP is ISLP × RSET, which has a value of 24 mV/dB.

IDET is the partially filtered demodulated signal, whose steady-

state average value is extracted through the subsequent

integration step.

VINT is the voltage intercept given by IINT × RSET, which has a

value of 1.44 V.

T is the effective time constant for the integration and is equal

to RSET × CFLT/1.35. The factor of 1.35 arises because of the

voltage gain of the buffer.

ISLP is the slope, which has a value of 5.75 μA/dB.

PIN is the input power in dBm (assuming 50 Ω input match).

IINT is the current intercept which, as previously noted, is

dependent on the RF waveform (not the envelope). Assuming

a sinusoidal input, IINT is 350 μA.

So the open-loop integration time constant can be written as

35

.

1

FLT

SET

OpenLoop

C

R

T

×

=

(8)

The current generated by the setpoint interface is simply

SET

SET

SET

R

V

I

=

(4)

To assess the closed-loop performance, refer to the block

diagram in Figure 28 and calculate the loop transfer function.

In general, the buffer time constant (τBUFFER) and the log amp

time constant (τLOGAMP) can be neglected, except in the case of

very high PA control function gains (> than 500 dB/V) and/or

very wide PA control port bandwidths. Assuming that the

frequency response of the output buffer and the log amp can be

neglected, the overall transfer function can be expressed as

where the

RSET resistor is 4.1 kΩ. The difference between this

current and IDET is applied to the loop filter capacitor CFLT. At

this point note that the inclusion of a filter resistor, RFLT, can be

helpful in improving the phase margin at low powers where the

PA control gain (that is, ∂POUT

/∂VAPC) is large, as is described

later in this section. For now assume that RFLT is zero. It follows

that the voltage appearing on this capacitor,

VFLT, is the time-

integral of the difference current.

() (

)

FLT

DET

SET

FLT

sC

I

I

s

V

−

=

(5)

POUT =

[

]

()

(

)

()

()

[]

FLT

PA

PA

SLP

FLT

PA

PA

INT

SLP

SET

sC

s

G

I

sC

s

G

I

I

I

τ

+

×

×

+

×

τ

+

×

×

−

×

+

1

35

.

1

1

)

1

(

1

35

.

1

30

(9)

FLT

INT

IN

SLP

SET

SET

sC

I

P

I

R

V

−

×

−

=

(6)

Here,

GPA is the PA control function gain ∂POUT/∂VAPC given in

dB/V, and the factor of −30 is due to the coupler.

The input power to the log amp, PIN, is given in dBm and

therefore is simply POUT of the PA minus the coupler value,

typically −30 dB, or PIN = POUT − 30.

The control output VAPC is slightly greater than this, since the gain

of the output buffer is ×1.35, plus a slight offset voltage. The

polarity is such that VAPC rises to its maximum value for any value

of VSET greater than the equivalent value of PIN. That is, the

AD8311 seeks to drive the RF power to its maximum value

whenever it falls below the setpoint. The use of exact integration

results in a dc error that is theoretically zero, and the logarithmic

detection law would ideally result in a constant response time

following a step change of either the setpoint or the power level if

the power-amplifier control function were likewise linear-in-dB.

This latter condition is rarely true, however, and it follows that in

practice the loop response time depends on the power level. This

effect can strongly influence the design of the control loop.

Equation 9 assumes that the next parasitic pole in the control

loop comes from the PA. For a typical PA, a 1 MHz pole is not

unusual, making this a good assumption. Therefore, except for

in the case of a very wide bandwidth on the PA control port

(>10 MHz),

the response time and stability of the control loop is

mainly determined by the characteristics of the PA. This is true

for both the gain and the phase response. It is essential to

understand both the magnitude and frequency response of the

power amplifier control port.

1

sCFLT

RFLT

+

IERR

ISET

VFLT

VAPC

1.35

s

τ

BUFFER

1 +

GPA (dB/V)

1 + s

τ

PA

POUT

–30dB

COUPLER

1 + s

τ

LOGAMP

ISLP PIN + IINT

+

_

IDET

PIN

Figure 28. Control Loop Block Diagram