MC44BC373C/374C Technical Data

High Speed I2C Compatible Bus

14.3 Levels Definition

In write mode, each ninth data bit (bits 9, 18, 27, 36, and 45) is an acknowledge bit (ACK) during which

the MCU sends a logic 1 and the Modulator circuit answers on the data line by pulling it low. Besides the

chip address, the circuit needs two or four data bytes for operation. The following sequences of data bytes

are the permitted incoming information:

After the chip address, two or four data bytes may be received.

•

If three data bytes are received, the third one is ignored.

•

If five or more data bytes are received, the fifth and following ones are ignored, and the last ACK

pulse is sent at the end of the fourth data byte.

11001010 (ACK) =$CA(hex) in write mode

Example 1

STA

CA

C1

C0

STO

Example 2

STA

CA

FM

FL

STO

Example 3

STA

CA

C1

C0

FM

FL

STO

Example 4

STA

CA

FM

FL

C1

C0

STO

With:

STA = Start condition

CA = Chip Address

FM = Frequency information, high order bits

FL = Frequency information, low order bits

C1 = Control information, high order bits

CO = Control information, low order bits

STO = Stop condition

SDA

...

0V

Vcc

Vih

Vil

dead band

1

2

3

4

5

6

7

8

9 10

14

11 12 13

45

44

15

19

16 17 18

STA

Chip Address ($CA)

ACK

ACK

First Data Byte (C1 or FM)

Data

ACK

Stop

SCL

SDA

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com