ADL5501

Rev. B | Page 24 of 2

8

1

6

2

5

3

4

ADL5501

VPOS

FLTR

RFIN

VRMS

ENBL

COMM

C3

(OPEN)

RFIN

VRMS

R3

0Ω

R5

(OPEN)

R1

(OPEN)

VPOS

C1

100pF

C2

0.1µF

R2

(OPEN)

R4

49.9Ω

C4

100nF

TO EDGE

CONNECTOR

TO EDGE

CONNECTOR

SW1

VPOS

ENBL

Figure 56. Evaluation Board Schematic

Table 5. Evaluation Board Configuration Options

Component

Description

Default Condition

GND, VPOS

Ground and supply vector pins.

Not applicable

C1, C2

Power supply decoupling. The nominal supply decoupling of 100 pF and 0.1 μF.

C1 = 100 pF (Size 0402)

C2 = 0.1 μF (Size 0402)

C3

Filter capacitor. The internal averaging capacitor can be augmented by placing additional

capacitance in C3.

C3 = open (Size 0402)

R2, R3, C4

Output filtering. The combination of the internal 100 Ω output resistance and C4 produces a low-

pass filter to reduce output ripple. The output can also be scaled down using the resistor divider

pads, R3 and R2. In addition, resistors and capacitors can be placed in C4 and R2 to load test VRMS.

R2 = open (Size 0402)

R3 = 0 Ω (Size 0402)

C4 = 100 nF (Size 0402)

R4, SW1

Device enable. When the switch is set toward the SW1 label, the ENBL pin is connected to VPOS,

and the ADL5501 is in operating mode. In the opposite switch position, the ENBL pin is grounded

(through the 49.9 Ω resistor), putting the device in power-down mode. While in this switch position,

the ENBL pin can be driven by a signal generator via the SMA labeled ENBL. In this case, R4 serves as

a termination resistor for generators requiring a 50 Ω match.

R4 = 49.9 Ω (Size 0402)

SW1 = toward SW1 label

R1, R5

Alternate interface. R1and R5 allow for VRMS and ENBL to be accessible from the edge

connector, which is used only for characterization.

R1 = open (Size 0402)

R5 = open (Size 0402)

Figure 57. Layout of Evaluation Board, Component Side

Figure 58. Layout of Evaluation Board, Circuit Side