(Preliminary)

PL610-01

1.8V to 3.3V, 1MHz to 130MHz XO IC

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/2/07 Page 2

KEY PROGRAMMING PARAMETERS (Optional)

CLK[0:1]

Output Frequency

Output Drive Strength

Programmable

Input/Output

(*: P is an Odd/Even Divider)

Where P = 6 bit

Three optional drive strengths

to choose from:

 Low: 4mA

 Std: 8mA (default)

 High: 16mA

One output pin can be configured

as:

 OE - input

 PDB - input

 CLK1 – output

PACKAGE PIN AND DIE PAD ASSIGNMENT

Pin Assignment

Name

DFN-6L

SOT23-6L

Type

Description

XIN, FIN

1

3

I

Crystal or Reference Clock input pin

OE, PDB,

CLK1

2

1

I/O

This programmable I/O pin can be configured as an Output

Enable (OE) input, Power Down input (PDB) input or CLK1

clock output. This pin has an internal 60KΩ pull up resistor

for OE and 10MΩ pull up resistor for PDB.

State

OE

PDB

0

Tri-state CLK

Power Down Mode

1 (default)

Normal mode

Normal mode

GND

3

2

P

GND connection

CLK0

4

6

O

Programmable Clock Output

VDD

5

5

P

VDD connection

Crystal Output pin

XOUT

6

4

O

Do Not Connect (DNC ) when FIN is present