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AEAS-7500 数据表(PDF) 2 Page - AVAGO TECHNOLOGIES LIMITED

部件名 AEAS-7500
功能描述  Ultra-Precision 16 bit Gray Code Absolute Encoder Module
PDF  8 Pages
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制造商  AVAGO [AVAGO TECHNOLOGIES LIMITED]
网页  http://www.avagotech.com
标志 AVAGO - AVAGO TECHNOLOGIES LIMITED

AEAS-7500 数据表(HTML) 2 Page - AVAGO TECHNOLOGIES LIMITED

  AEAS-7500 Datasheet HTML 1Page - AVAGO TECHNOLOGIES LIMITED AEAS-7500 Datasheet HTML 2Page - AVAGO TECHNOLOGIES LIMITED AEAS-7500 Datasheet HTML 3Page - AVAGO TECHNOLOGIES LIMITED AEAS-7500 Datasheet HTML 4Page - AVAGO TECHNOLOGIES LIMITED AEAS-7500 Datasheet HTML 5Page - AVAGO TECHNOLOGIES LIMITED AEAS-7500 Datasheet HTML 6Page - AVAGO TECHNOLOGIES LIMITED AEAS-7500 Datasheet HTML 7Page - AVAGO TECHNOLOGIES LIMITED AEAS-7500 Datasheet HTML 8Page - AVAGO TECHNOLOGIES LIMITED  
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Signal-channels A1-A11
The photocurrent of the photodiodes is fed into a tran-
simpedance amplifier. The analog output of the amplifier
hasavoltageswingof(dark/light)about1.3V. Everyoutput
istransformedbyprecisioncomparatorsintodigitalsignals
(D1-D11). The threshold is at VDD/2(=Analog-reference),
regulated by the monitor channel.
Monitor Channel with LED Control at pins LEDR and LERR
The analog output signal of the monitor channel is regu-
lated by the LED current. An external bipolar transistor(to
be connected by user) sets this level to VDD/2 (control
voltage at pin LEDR). Thus the signal swing of each output
is symmetrical to VDD/2(=Analog-reference)
The error bit at pin LERR is triggered if theVe of the internal
bipolar transistor is larger than VDD/2
Signals Channels A0, A09 with signal conditioning and cali-
bration
Thesetwochannelsgiveoutasineandcosinewave,which
are90degreephaseshifted. Thesesignalshaveamplitudes,
whicharealmostconstantduetotheLEDcurrentmonitor-
ing. Due to amplifier mismatch and mechanical misalign-
ment the signals have gain and offset errors. These errors
areeliminatedbyanadaptivesignalconditioningcircuitry.
The conditioning values are on-chip preprogrammed by
factory. The analog output signals of A0 and A09 are sup-
plied as true-differential voltage with a peak to peak value
of 2.0V at the pins A09P, A09N, A0P, A0N.
Interpolator for Channels A0,A09
The interpolator generates the digital signals D0,D09 and
D-1 to D-4. The interpolated signals D-1 to D-4 extend
the 12 bit Gray code of the signals D11….D0 to form a 16
bit Gray code.
D0 and D09 are digitized from A0 and A09. The channels
A0-A11 and A09 have very high dynamic bandwidth,
which allows a real time monotone 12Bit Gray code at
12000 RPM.
The interpolated 16 bit Gray code can be used up to
1000RPM only. At more than 1000RPM, only the 12 bit
Gray code from the MSB side can be used.
LSB gray code Correction (Pin KORR)
This function block synchronizes the switching points for
the 11 bit gray code of the digital signals D1 to D11 with
D0 and D09 (digitized signal of A0 and A09).
The accuracy of the complete 12 bit gray is defined by
the precision of the signals D0/D09. As these two signals
are generated by the gain and offset conditioned analog
signals A0 and A09, they are very precise.
This Gray code correction only works for the full 12 bit
(4096 steps per revolution).
The correction is not for the 4 excess interpolated bits of
the16bitGraycode. Graycodecorrectioncanbeswitched
on or off by putting the pin KORR =1(on) or =0(off).
MSBINV and DOUT pins
The serial interface consists of a shift register. The most
significant bit, MSB(D11) will always be sent first to DOUT.
The MSB can be inverted (change code direction) by using
pin MSBINV.
DIN and NSL pins
The Serial input DIN allows the configuration as ring reg-
ister for multiple transmissions or for cascading 2 or more
encoders. DIN is the input of the shift register that shifts
the data to DOUT.
TheNSLpincontrolstheshiftregister,toswitchitbetween
load (1) or shift(0) mode. Under load mode, DOUT will give
the logic of the MSB, i.e. D11.
Undershiftmode(0),coupledwiththeSCL,theregisterwill
be clocked, and gives out the serial word output bit by bit.
As the clock frequency can be up to 16 MHz, the transmis-
sion of the full 16 bit word can be done within 1 µs.
Valid data of DOUT should be read when the SCL clock is
low. Please refer to timing diagram Figure 4.



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