TDA4AEN...Q1 datasheet(142/236 Pages) TI

142 / 236 page

6.9.5.13 GPMC

For more details about features and additional description information on the device General-Purpose Memory

Controller, see the corresponding subsections within Signal Descriptions and Detailed Description sections.

Table 6-64 presents timing conditions for GPMC.

Table 6-64. GPMC Timing Conditions

PARAMETER

MIN

MAX UNIT

INPUT CONDITIONS

SRI

Input slew rate

1.65

V/ns

OUTPUT CONDITIONS

Output load capacitance

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of each trace

133MHz Synchronous Mode

140

360

All other modes

140

720

td(Trace Mismatch

Delay)

Propagation delay mismatch across all traces

200

For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the

device TRM.

6.9.5.13.1 GPMC and NOR Flash — Synchronous Mode

Table 6-65 and Table 6-66 present timing requirements and switching characteristics for GPMC and NOR Flash -

Synchronous Mode.

Table 6-65. GPMC and NOR Flash Timing Requirements — Synchronous Mode

see Figure 6-47, Figure 6-48, and Figure 6-51

NO.

PARAMETER

DESCRIPTION

MODE(4)

MIN

MAX

MIN

MAX

UNIT

GPMC_FCLK =

100MHz(1)

GPMC_FCLK =

133MHz(1)

F12 tsu(dV-clkH)

Setup time, input data

GPMC_AD[15:0] valid before output

clock GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.61

0.92

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

0.86

3.41

F13 th(clkH-dV)

Hold time, input data

GPMC_AD[15:0] valid after output

clock GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.09

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.09

F21 tsu(waitV-clkH)

Setup time, input wait

GPMC_WAIT[j](2) (3) valid before

output clock GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.61

0.92

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

0.86

3.41

F22 th(clkH-waitV)

Hold time, input wait

GPMC_WAIT[j](2) (3) valid after

output clock GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.09

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.09

(1)

GPMC_FCLK select

TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

142

Submit Document Feedback

Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1

TDA4AEN...Q1 数据表(PDF) 142 Page - Texas Instruments

TDA4AEN...Q1 数据表(HTML) 142 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

TDA4AEN...Q1 数据表(PDF) 142 Page - Texas Instruments

TDA4AEN...Q1 数据表(HTML) 142 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载