PPC405GPR-3JB266 datasheet(6/57 Pages) AMCC

部件名	PPC405GPR-3JB266

功能描述	Power PC 405GPr Embedded Processor

PDF	57 Pages

Scroll/Zoom	100%

制造商	AMCC [Applied Micro Circuits Corporation]

网页	http://www.amcc.com

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405GPr – Power PC 405GPr Embedded Processor

AMCC

Revision 2.04 – September 7, 2007

Data Sheet

PPC405GPr Embedded Controller Functional Block Diagram

The PPC405GPr is designed using the IBM® Microelectronics Blue LogicTM methodology in which major functional

blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent

way to create complex ASICs using IBM CoreConnectTM Bus Architecture.

PPC405

Processor Core

DOCM

IOCM

DCU

ICU

OCM

Control

OCM

SRAM

DCR Bus

16KB

On-chip Peripheral Bus (OPB)

GPIO

IIC

UART

MAL

Ethernet

DMA

Bridge

Processor Local Bus (PLB)

SDRAM

PCI Bridge

Code

Decompression

External

Bus

Controller

Clock

Control

Reset

Power

Mgmt

JTAG

Trace

Timers

MMU

MII

Controller

OPB

Interrupt

Controller

Arb

32-bit addr

32-bit data

13-bit addr

32-bit data

External

Bus Master

Controller

Universal

I-Cache

D-Cache

(4-Channel)

(CodePack

™)

66 MHz max (async)

DCRs

33 MHz max (sync)

16KB

Arb

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