CAT310 datasheet(4/11 Pages) CATALYST

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CAT310

Doc No. 25087, Rev. 1

Characteristics subject to change without notice

PIN DESCRIPTIONS

VCC is the supply input for the internal logic

and is compatible with both 3.3V and 5V

systems. The logic is held in a reset state until

VCC exceeds 2.5V. It is recommended that a

small bypass ceramic capacitor (1uF) be

placed between VCC and GND pins on the

device.

SIN is the CMOS logic pin for delivering the

serial input data stream into the internal 10-bit

shift register. The most recent or last data

value in the serial stream is used to configure

the state of output channel “zero” (OUT0).

During the initial power up sequence all

contents of the shift register are reset and

cleared to zero.

SCLK is the CMOS logic pin used to clock

the internal shift register. On each rising edge

of clock, the serial data will advance through

one stage of the shift register.

XLAT is the CMOS logic input used to

transfer data from the 10-bit shift register into

the output channel latches. An internal pull-

down current of 10 microampere is present on

this pin. When XLAT is low, the state of each

output channel remains unchanged. When

XLAT is driven high, the contents of the shift

channels. An external pull-up resistance of

10k

Ω or less is adequate for logic high.

PGND, GND pins should be connected to

the ground on the PCB.

BLANK is the CMOS logic input (active high)

used to temporarily disable all outputs. An

internal pull-up current of 10 microampere is

present on this pin. The BLANK pin must be

driven to a logic low in order for channel outputs

to resume normal operation. An external pull-

down resistance of 10k

Ω or less is adequate for

logic low.

SOUT is the CMOS logic output used for daisy

chain applications. The serial output data

stream is fed from the last stage of the internal

10-bit shift register. On each rising edge of the

clock, the SOUT value will be updated. The

data value present on this pin is identical to the

data value being used for configuring the state

of output channel nine (OUT9). At initial power

up, the SOUT data stream will contain all

zeroes until the shift register has been fully

loaded.

VBATT input monitors the battery voltage. If an

over-voltage, above 19V typical, is detected, all

outputs are disabled. Upon conclusion of the

over-voltage condition, all outputs resume

normal operation. The current drawn by the

VBATT pin is less than 1 microampere during

normal operation.

OUT0-OUT9 are the ten LED outputs

connected internally to the switch N-channel

FETs. They sink currents up to 50mA per

channel and can withstand transients up to 40V

compatible with automotive “load dump”. The

output on-resistance is 5

Ω, and the off-

resistance is 5M

Ω.

PIN TABLE

Pin Number

Pin Name

Description/Function

SCLK

Clock input for the data shift register.

XLAT

Control input for the data latch.

SIN

Serial data input.

SOUT

Serial data output.

GND

Ground.

6-10

OUT4 - OUT0

Open drain outputs.

11-15

OUT9 - OUT5

Open drain outputs.

PGND

Ground for LED driver outputs.

VBATT

Battery sense input.

VCC

Power supply voltage for the logic

BLANK

Blank input. When BLANK is high, all the output drivers are turned off.

N.C.

No connect.

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