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SN54ABT16853 数据表(PDF) 6 Page - Texas Instruments |
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SN54ABT16853 数据表(HTML) 6 Page - Texas Instruments |
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6 / 11 page ![]() SN54ABT16853, SN74ABT16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C SN54ABT16853 SN74ABT16853 UNIT MIN MAX MIN MAX MIN MAX t Pulse duration LE high or low 8.5 8.5 8.5 ns tw Pulse duration CLR low 4 4 4 ns t Setup time A, B, and PARITY before LE ↓ 10 10 10 ns tsu Setup time CLR before LE ↓ 0 0 0 ns th Hold time A, B, and PARITY after LE ↓ 0 0 0 ns th Hold time CLR after LE ↓ 0 0 0 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C SN54ABT16853 SN74ABT16853 UNIT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX tPLH AorB BorA 1.5 2.5 3.3 1.5 4.2 1.5 4.1 ns tPHL A or B B or A 2 3.1 3.9 2 4.5 2 4.3 ns tPLH AorOE PARITY 2 4.6 5.9 2 7.3 2 7.1 ns tPHL A or OE PARITY 2 4.8 6.2 2 7.6 2 7.2 ns tPLH CLR ERR 2 3.7 5.1 2 5.9 2 5.7 ns tPZH OE AorB 2 3.9 4.9 2 5.8 2 5.6 ns tPZL OE A or B 2.5 4.3 5.1 2.5 6.2 2.5 6 ns tPHZ OE AorB 2 3.6 4.5 2 5.5 2 5.4 ns tPLZ OE A or B 1.5 3 3.8 1.5 4.7 1.5 4.3 ns tPZH OE PARITY 2 3.6 5 2 5.8 2 5.7 ns tPZL OE PARITY 2.5 4.4 5.8 2.5 6.7 2.5 6.5 ns tPHZ OE PARITY 1.5 3.2 4 1.5 4.8 1.5 4.7 ns tPLZ OE PARITY 1.5 2.9 3.7 1.5 4.2 1.5 4.1 ns tPLH LE ERR 2 3.5 4.2 2 5 2 4.8 ns tPHL LE ERR 2 3.4 4.4 2 5.2 2 4.9 ns tPLH A B or PARITY ERR 2 4.5 6.3 2 7.5 2 7.2 ns tPHL A, B, or PARITY ERR 2 4.8 6.3 2 7.7 2 7.4 ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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