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 2006 Semtech Corp.

www.semtech.com

SC486

POWER MANAGEMENT

Layout Guidelines

One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and

maximize heat dissipation. The IC ground reference, VSSA, should be connected to PGND1 and PGND2 as a star

connection at the thermal pad, which in turn is connected using 4 vias to the ground plane. All components that are

referenced to VSSA should connect to it directly on the chip side, and not through the ground plane.

VDDQ: the feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate

drives. Route the feedback trace in a quiet layer if possible from the output capacitor back to the chip.

Chip supply decoupling capacitors (VCCA, VDDP) should be located next to the pins (VCCA and VSSA, VDDP and

PGND1) and connected directly to them on the same side.

VTT: output capacitors should be located right across the VTT output pins (VTT and PGND2) as close as possible to

the part to minimize parasitics.

The switcher power section should connect directly to the ground plane(s) using multiple vias as required for current

handling (including the chip power ground connections). Power components should be placed to minimize loops and

reduce losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not

use “minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the

gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most

critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current

handling requirement (and to reduce parasitics) if routed on more than one layer. Current sense connections must

always be made using Kelvin connections to ensure an accurate signal.

We will examine the SC486 DDR2 reference design used in the Design Procedure section while explaining the layout

guidelines in more detail.

+

C14

220u/15m

VDDQ

+

C13

220u/15m

VDDQ

C17

1u

C16

10u

VTT

C12

1u

R2

10R

5VSUS 5VRUN

C3

no-pop

R7 10R

REF

R6

10R

C9

1u

R4 10R

C2

1u

R5 4k64

R8

23k2

PGOOD

VBAT

C11

1n

C1

no-pop

C10

no-pop

R9 0R

VDDQ

R10 13k0

C18

1u

C4

0.1uF

D1

R3 470k

5VSUS

C5

2n2/50V

R1

715k

VBAT

L1

1u5

C15

10u

PGND1

18

REF

8

EN/PSV

1

TON

2

VDDQS

3

VCCA

5

FB

6

PGD

7

VSSA

4

PGND2

17

DL

19

VDDP

20

ILIM

21

LX

22

DH

23

BST

24

VTTEN

11

VTT

15

PGND2

16

VTTIN

12

VTTIN

13

VTT

14

VTTS

10

COMP

9

U1

SC486

Q1

IRF7811AV

Q2

FDS6676S

C6

0u1/25V

C7

10u/25V

C8

10u/25V

Figure 4: DDR2 Reference Design and Layout Example

Sample DDR2 Design Using SC486

VBAT = 9V to 19.2V

VDDQ = 1.8V @ (8+2)A

VTT = 0.9V @ 2A