4

HV5522/HV5530/HV5622/HV5630

Functional Block Diagram

Function Table

Inputs

Outputs

Function

Shift Reg

HV Outputs

Data Out

12…32

1

2…32

*

All on

X

X

X

L

L

*

*…*On

On…On

*

All off

X

X

X

L

H

*

*…*

Off

Off…Off

*

Invert mode

X

X

L

H

L

*

*…**

*…**

Load S/R

H or L

↓

LH

H

H or L *…**

*…**

XH or L

↑

HH

*

*…**

*…**

XH or L

↑

HL

*

*…**

*…**

L

↓

HH

H

L

*…*

Off

*…**

H

↓

H

HHH

*…*On*…**

Notes:

H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transistion.

* = dependent on previous stage’s state before the last CLK ↓ or last LE high.

Data

CLK

LE

BL

POL

Transparent

Latch mode

Load

Latches

Polarity

Blanking

Latch Enable

Data Input

Clock

Data Out

32-Bit

Shift

Register

(Outputs 3 to 30

not shown)

Latch

Latch

Latch

Latch