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POWER MANAGEMENT

SC1210

the Phase Node during the top FET turn-off due to para-

sitic inductance in the switching loop. The spike could

be minimized with a careful PCB layout. In those applica-

tions with TO-220 package FETs, it is recommended to

use a clamping diode on the DRN pin to mitigate the

impact of the excessive phase node negative spike.

Filters for Supply Power

Filters for Supply Power

Filters for Supply Power

Filters for Supply Power

Filters for Supply Power

For VREG pin of the SC1210, it is recommended to use

a 1uF to 4.7uF, 25V rating ceramic capacitor for

decoupling.

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LAYYYYYOUT GUIDELINES

OUT GUIDELINES

OUT GUIDELINES

OUT GUIDELINES

OUT GUIDELINES

The switching regulator is a high di/dt power circuit. Its

Printed Circuit Board (PCB) layout is critical. A good lay-

out can achieve an optimum circuit performance while

minimized the component stress, resulting in better sys-

tem reliability. For a multi-phase voltage regulator, the

SC1210 driver, FETs, inductor, and supply decoupling ca-

pacitors in each phase have to be considered to yield a

proper PCB layout.

For the SC1210 driver, the following guidelines are typi-

cally recommended during PCB layout:

1. Place the SC1210 close to the FETs for shortest gate

drive traces and ground return paths.

2. Connect bypass capacitors as close as possible to

decoupling pins (VREG and VIN) and PGND. The trace

length of the decoupling capacitor on VREG pin should

be no more than 0.2” (5mm).

3. Locate the components of the bootstrap circuit close

to the SC1210.

4. Provide a proper decoupling for the FETs to reduce

the inductive kick seen by the DRN pin.

Applications Information (Cont.)