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© 2005 Semtech Corp.

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POWER MANAGEMENT

SC2516

Applications Information (Cont.)

The control model of SC2516 VDDQ and GMCH section

can be depicted in Fig. 1. This model can also be used in

Spice kind of simulator to generate loop gain Bode plots.

The bandgap reference is 1.25 V and trimmed to +/-1%

accuracy. The desired output voltage can be achieved

by setting the resistive divider network, R1 and R2.

The error amplifier is transconductance type with fixed

gain of:

The compensation network includes a resistor and a ca-

pacitor in series, which terminates from the output of

the error amplifier to the ground. The PWM gain is inver-

sion of the ramp amplitude, and this gain is given by:

where the ramp amplitude (peak-to-peak) is 0.55 volts .

The total control loop-gain can then be derived as

follows:

Ts

() T o

1s R

. C

.

sR

. C

.

.

1s R c

.

C o

.

1s R c C o

.

L

R o

.

s

2

L

. C

o

.

1

R c

R o

.

.

where

The task here is to properly choose the compensation

network for a nicely shaped loop-gain Bode plot. The

following design procedures are recommended to accom-

plish the goal:

(1) Calculate the corner frequency of the output filter:

(2) Calculate the ESR zero frequency of the output filter

capacitor:

(3) Check that the ESR zero frequency is not too high.

If this condition is not met, the compensation structure

may not provide loop stability. The solution is to add

some electrolytic capacitors to the output capacitor bank

to correct the output filter corner frequency and the ESR

zero frequency. In some cases, the filter inductance may

also need to be adjusted to shift the filter corner

frequency. It is not recommended to use only high fre-

quency multi-layer ceramic capacitors for output filter.

(4) Choose the loop gain cross over frequency (0 dB fre-

quency). It is recommended that the crossover frequency

is always less than one fifth of the switching frequency :

If the transient specification is not stringent, it is better

to choose a crossover frequency that is less than one

tenth of the switching frequency for good noise immunity.

The resistor in the compensation network can then be

calculated as:

when

Fig. 1. SC2516 small signal model.

C

Vbg

1.25Vdc

L

Rc

R

Co

Gpwm

EA

Ro

R2

Vin

R1

5

<

G pwm

1

V ramp

⋅

⋅

R

⋅

⎛

⎜

⎝

⎞

⎠

⋅

:=

1

2

π

⋅

⋅

⋅

:=

1

2

π

⋅

⋅

:=

5

≤

R

1

⋅

⋅

⎛

⎜

⎝

⎞

⎠

2

⋅

⎛

⎜

⎝

⎞

⎠

⋅

⎛

⎜

⎝

⎞

⎠

⋅

:=

<

<

0.001 A

⋅

V

:=

Compensation design of the VDDQ Channel

Compensation design of the VDDQ Channel

Compensation design of the VDDQ Channel

Compensation design of the VDDQ Channel

Compensation design of the VDDQ Channel