AI01822

3V

High Speed

0V

1.5V

2.4V

Standard

0.4V

2.0V

0.8V

Figure 3. AC Testing Input Output Waveform

AI01823B

1.3V

OUT

CL

CL = 30pF for High Speed

CL = 100pF for Standard

CL includes JIG capacitance

3.3k

Ω

1N914

DEVICE

UNDER

TEST

Figure 4. AC Testing Load Circuit

High Speed

Standard

Input Rise and Fall Times

≤ 10ns

≤ 20ns

Input Pulse Voltages

0 to 3V

0.4V to 2.4V

Input and Output Timing Ref. Voltages

1.5V

0.8V and 2V

Table 5. AC Measurement Conditions

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Capacitance

6

pF

Output Capacitance

12

pF

Note: 1. Sampled only, not 100% tested.

°C, f = 1 MHz )

Two Line Output Control

BecauseEPROMs are usually used in largermem-

ory arrays, this product features a 2 line control

function which accommodates the use of multiple

memory connection. The two line control function

allows:

a. the lowest possible memory power dissipation,

b. complete assurance that output bus contention

will not occur.

For the most efficient use of thesetwo control lines,

E should be decoded and used as the primary

device selecting function, while G should be made

a common connection to all devices in the array

and connected to the READ line from the system

control bus. This ensures that all deselected mem-

ory devices are in their low power standby mode

and that the output pins are only active when data

is required from a particular memory device.

System Considerations

The power switching characteristics of Advanced

CMOS EPROMs require careful decoupling of the

ments that are of interest to the system designer :

the standby current level, the active current level,

and transient current peaks that are produced by

the falling and rising edges of E. The magnitude of

transientcurrent peaks is dependenton the capaci-

tive and inductive loading of the device at the

output.

4/15

M27C1024