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SC4612STRT 数据表(PDF) 13 Page - Semtech Corporation |
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SC4612STRT 数据表(HTML) 13 Page - Semtech Corporation |
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13 / 24 page ![]() 13 2007 Semtech Corp. www.semtech.com SC4612 POWER MANAGEMENT The design guidelines are as following: 1. Set the loop gain crossover frequency w C for given switching frequency. 2. Place an integrator at the origin to increase DC and low frequency gains. 3. Select w Z1 and wZ2 such that they are placed near wO to dampen peaking; the loop gain should cross 0dB at a rate of -20dB/dec. 4. Cancel w ESR with compensation pole wP1 (wP1 = wESR ). 5. Place a high frequency compensation pole w P2 at half the switching frequency to get the maximum attenuation of the switching ripple and the high frequency noise with adequate phase lag at w C. Application Information (Cont.) 0dB Gd T ωZ1 ω Z2 p1 p2 c ESR ω o ω ω ω ω Loop gain T(s) Figure 2. Simplified asymptotic diagram of buck power stage and its compensated loop gain. Table 1 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 Frequency, (kHz) Switching Frequency, F SW vs. COSC. |
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