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SC453TSTRT 数据表(PDF) 9 Page - Semtech Corporation |
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SC453TSTRT 数据表(HTML) 9 Page - Semtech Corporation |
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9 / 23 page ![]() 9 © 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC453 Pin Configuration Pin Descriptions (Cont.) Pin# Pin Name Pin Function 11 VID3 VID input. 12 VID2 VID input. 13 VID1 VID input. 14 VID0 VID least significant bit main controller voltage programming DAC input. 15 SS Soft-start. An external cap defines the soft-start ramp. 16 PG_DEL Delayed power good - open drain output. When the Main Converter Output approaches and stays within ± 14% of the VID_DAC setting, and the t CPU_PWRGD period has terminated. This signal is pulled high by an external resistor. 17 CORE Main CORE converter output feedback to the power good generator. A small RC filter should be used to filter out any HF component to prevent faulty trip condition. 18 DAC Main controller digital-to-analog output. 19 GND Analog ground. 20 REFIN Core Comparator reference input pin. Connect to DAC. 21 VCCA 5V supply for precision analog circuitry. 22 CLRF Current limit reference input pin 23 CMP Core Comparator input pin. 24 CL Current limit input pin. 25 EN Enable - active high. This is capable of accepting a 5.0V signal level. 26 PGND Power ground. Connect to the synchronous FET power ground. 27 BG Output drive for the synchronous (low-side) FET. 28 V5 5VDC supply for the driver. A capacitor should be connected from V5 to GND. |
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