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 2005 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC2602L

Block Diagram

Synchronous Buck Converter

The output rail is regulated by a synchronous, voltage-

mode pulse width modulated (PWM) controller. This

section has all the features required to build a high effi-

ciency synchronous buck converter, including “Power

Good” flag, shut-down, and cycle-by-cycle current limit.

The output voltage of the synchronous converter is set

and controlled by the output of the error amplifier. The

external resistive divider reference voltage is derived from

an internal trimmed-bandgap voltage reference (See Fig.

1). The inverting input of the error amplifier receives its

voltage from the SENSE pin.

The internal oscillator uses an on-chip capacitor and

trimmed precision current sources to set the oscillation

frequency to 200kHz. The triangular output of the oscil-

lator sets the reference voltage at the inverting input of

the comparator. The non-inverting input of the compara-

tor receives it’s input voltage from the error amplifier.

When the oscillator output voltage drops below the er-

ror amplifier output voltage, the comparator output goes

high. This pulls DL low, turning off the low-side FET, and

DH is pulled high, turning on the high-side FET (once

the cross-current control allows it). When the oscillator

voltage rises back above the error amplifier output volt-

age, the comparator output goes low. This pulls DH low,

turning off the high-side FET, and DL is pulled high, turn-

ing on the low-side FET (once the cross-current control

allows it).

As SENSE increases, the output voltage of the error

amplifier decreases. This causes a reduction in the on-

time of the high-side MOSFET connected to DH, hence

lowering the output voltage.

Under Voltage Lockout

The under voltage lockout circuit of the SC2602L as-

sures that the high-side MOSFET driver outputs remain

in the off state whenever the supply voltage drops below

set parameters. Lockout occurs if V

Normal operation resumes once V

Over-Voltage Protection

The over-voltage protection pin (OVP) is high only when

the voltage at SENSE is 20% higher than the target value

programmed by the external resistor divider. The OVP

pin is internally connected to a PNP’s collector.

Power Good

The power good function is to confirm that the regulator

outputs are within +/-10% of the programmed level.

PWRGD remains high as long as this condition is met.

PWRGD is connected to an internal open collector NPN

transistor.

Theory of Operation

+10%

-10%

0.8V

+20%

DRVH

DRVH

Cross

Current

Control

DRVL

DRVL

S

R

QB

S

R

QB

Under

Voltage

Over Current

Oscillator

One Shot

PWM

Fault

Error Amp

Vbg

Vbg

VCC

VCC

200uA

10uA

1.5uA

0.6V

0.8V

VCC

PWRGD

OVP

COMP

SENSE

SS/SHDN

PGND

OCSET

BSTH

PHASE

BSTL

DL

DH

GND