ST7LITE2 datasheet(96/133 Pages) STMICROELECTRONICS

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ST7LITE2

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OPERATING CONDITIONS (Cont’d)

13.3.4.2 RC oscillator and PLL characteristics (tested for TA = -40 to +85°C) @ VDD = 2.7 to 3.3V

Notes:

1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a

decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.

2. Data based on characterization results, not tested in production

3. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 23.

4. Guaranteed by design.

5. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy

6. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 12 on page 24.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fRC

Internal RC oscillator fre-

quency 1)

RCCR = FF (reset value), TA=25°C, VDD= 3.0V

560

kHz

RCCR=RCCR13) ,TA=25°C,VDD= 3V

700

ACCRC

Accuracy of Internal RC

oscillator when calibrated

with RCCR=RCCR12)3)

TA=25°C,VDD=3V

-2

TA=25°C,VDD=2.7 t 3.3V

-25

+25

TA=-40 to +85°C,VDD=3V

-15

IDD(RC)

RC oscillator current con-

sumption

TA=25°C,VDD=3V

7002)

µA

tsu(RC)

RC oscillator setup time

TA=25°C,VDD=3V

103)

µs

fPLL

x4 PLL input clock

0.72)

MHz

tLOCK

PLL Lock time6)

2ms

tSTAB

PLL Stabilization time6)

4ms

ACCPLL

x4 PLL Accuracy

fRC = 1MHz@TA=25°C,VDD=2.7 to 3.3V

0.15)

fRC = 1MHz@TA=40 to +85°C,VDD= 3V

0.15)

tw(JIT)

PLL jitter period

fRC = 1MHz

1254)

µs

JITPLL

PLL jitter (

∆f

CPU/fCPU)1

IDD(PLL)

PLL current consumption TA=25°C

1902)

µA

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