ST7LITE2 datasheet(131/133 Pages) STMICROELECTRONICS

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17 REVISION HISTORY

Table 28. Revision History

Date

Revision

Description of Changes

30-August-

2004

Updated Figure 62. Typical IDD in WAIT vs. fCPU with correct data

Added data for Fcpu @ 1MHz into Section 13.4.1 Supply Current table.

EnabledProgramming Capability for EMU3, Table 26

Reset delay in section 11.1.3 on page 53 changed to 30µs

Altered note 1 for section 13.2.3 on page 94 removing references to RESET

Removed sentence relating to an effective change only after overflow for CK[1:0], page 61

MOD00 replaced by 0Ex in Figure 37 on page 58

Added Note 2 related to Exit from Active Halt, section 11.2.5 on page 60

Changed section 11.4.2 on page 71

Changed section 11.4.3.3 on page 74

Added illegal opcode detection to page 1, section 7.6 on page 30, section 12 on page 87

Clarification of Flash read-out protection, section 4.5.1 on page 14

Added note 4 and description relating to Total Percentage in Error and Amplifier Output Offset

Variation to the ADC Characteristics subsection and table, page 120

Added note 5 and description relating to Offset Variation in Temperature to ADC Characteris-

tics subsection and table, page 120

fPLL value of 1MHz quoted as Typical instead of a Minimum in section 13.3.4.1 on page 97

Updated fSCK in section 13.10.1 on page 115 to fCPU/4 and fCPU/2

CorrectedfCPU in SLOW and SLOW WAIT modes in section 13.4.1 on page 101

Max values updated for ADC Accuracy, page 118

Socket Board development kit details added in Table 27 on page 126

Notes indicating that PB4 cannot be used as an external interrupt in HALT mode, section 16.6

on page 132 and Section 8.3 PERIPHERAL INTERRUPTS

-Removed “optional” referring to VDD in Figure 5 on page 13

-Changed FMP_R option bit description in section 15.1 on page 124

-Added “CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE” on page 132

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