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TLK1101ERGPR 数据表(PDF) 2 Page - Texas Instruments |
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TLK1101ERGPR 数据表(HTML) 2 Page - Texas Instruments |
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2 / 28 page ![]() www.ti.com BLOCK DIAGRAM Output Buffer Output Driver 50W VCC ControlSettings 4-Bit Input Threshold De-emphasis OutputSwing InputBandwidth LOS AssertLevel Power-On Reset - Band GapVoltage Referenceand BiasCurrent Generation 2-WireInterface & ControlLogic SDA SCL DIS DIN+ DIN- SDA SCL DIS DOUT+ DOUT- Equalizer Stage InputBuffer with Selectable Bandwidth Offset Cancellation LN 0 LN0 LN1 LN1 8-BitRegister 2-Bit 4-Bit + Select 7-Bit + Select LossofSignal Detection LOS VCC GND LOSR LOSR SWG SWG LOSL LOSL VTH VTH DE 0 DE0 DE 1 DE1 4-Bit SEL_RATE 7-BitRegister SEL_LOSL 8-BitRegister 50W 50W VCC 50W TLK1101E SLLS845A – AUGUST 2007 – REVISED OCTOBER 2007 The output can be disabled using the DIS pin. The DIS and the LOS pin can be connected together to implement a squelch function. The de-emphasis, the output voltage swing, the input threshold voltage, the output disable, and the LOS assert levels and ranges can alternatively be set using the two-wire serial interface through the SCL and SDA pins. The external pin configuration is the default device setup method. The active device control method is selected through register address 0 bit 0 (see Table 4 and Table 20). The two-wire serial interface also allows for the control of the input bandwidth to optimize the device performance for various data rates. The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal swings as high as 1600mVp-p differential. The low-frequency cut-off is low enough to support low-frequency control signals such as SAS and SATA out-of-band (OOB) signals. A simplified block diagram of the TLK1101E is shown in Figure 1. This compact, low power, 11.3-Gbps equalizer consists of a high-speed data path with offset cancellation block combined with an analog input threshold selection circuitry, a loss of signal detection block, a two-wire interface with a control-logic block, a bandgap voltage reference, and a bias current generation block. Figure 1. Simplified Block Diagram of the TLK1101E 2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TLK1101E |
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