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SC411

POWER MANAGEMENT

As shown below, VOUT should be routed away from noisy traces (such as BST, DH, DL and LX) and in a quiet layer (if

possible) to the output capacitor(s).

Figure 7: VOUT Sense Trace Routing

Next, the schematic in Figure 8 below shows the power section. The highest di/dts occur in the input loop (highlight-

ed in red) and thus this loop should be kept as small as possible.

Figure 8: Power Section and Input Loop

The input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce EMI. Use

large copper pours to minimize losses and parasitics. See Figure 9 for an example.

VOUT

+

C6

220u/25m

VOUT

VOUT

1

VCCA

2

FB

3

PGD

4

VDDP

9

ILIM

10

LX

11

DH

12

U1

SC411

C5

56p

0402

0402

0402

+

C7

220u/25m

7343

7343

R3

20k0

R5

14k3

Q1

IR F 7 81 1A V

C2

2n 2/50 V

VBAT

L1

2u 2

+

C6

220 u/2 5 m

VO U T

Q2

F D S 6 67 6S

C3

0u1 /25V

04 02

060 3

C4

1 0u/2 5 V

1 210

+

C7

2 20u /25 m

734 3

7 343