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SC411MLTRT 数据表(PDF) 17 Page - Semtech Corporation |
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SC411MLTRT 数据表(HTML) 17 Page - Semtech Corporation |
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17 / 27 page ![]() 17 © 2007 Semtech Corp. www.semtech.com SC411 POWER MANAGEMENT Layout Guidelines Figure 4: Reference Design One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and maximize heat dissipation. The IC ground reference, VSSA, and the power ground pin, PGND, should both connect directly to the device thermal pad. The thermal pad should connect to the ground plane(s) using multiple vias. The VOUT feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate drives. Route the feedback trace in a quiet layer (if possible) from the output capacitor back to the chip. All compo- nents should be located adjacent to their respective pins with an emphasis on the chip decoupling capacitors (VCCA and VDDP) and the components that are shown connecting to VSSA in the above schematic. Make any ground con- nections simply to the ground plane. Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling (in- cluding the chip power ground connections). Power components should be placed to minimize loops and reduce loss- es. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use “minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling requirements (and to reduce parasitics) if routed on more than one layer. Current sense connections must always be made using Kelvin connections to ensure an accurate signal, with the current limit resistor located at the device. We will examine the reference design used in the Design Procedure section while explaining the layout guidelines in more detail. VOUT C8 1nF VBAT R1 1M PGOOD Q1 IRF7811AV C10 1uF R4 7k87 C1 0u1 D1 C2 2n2/50V VBAT 5VSUS L1 2u2 + C6 220u/25m VOUT R2 10R 5VSUS VOUT 1 VCCA 2 FB 3 PGD 4 VDDP 9 ILIM 10 LX 11 DH 12 U1 SC411 Q2 FDS6676S C5 56p 0402 0402 0402 0402 0402 0402 0603 0603 0402 0603 SOD323 0402 C3 0u1/25V 0603 C4 10u/25V 1210 + C7 220u/25m VBAT = 8V to 20V VOUT = 1.2V @ 6A 7343 7343 C9 1uF R3 20k0 R5 14k3 |
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