SC621

5

Electrical Characteristics (continued)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

LDO Electrical Specifications

(continued)

Load Regulation

ΔV

LOAD

V

LDO1

= 3.3V, V

IN

= 3.7V,

I

LDO1

= 1mA to 100 mA

25

mV

V

LDO2

= 1.8V, V

IN

= 3.7V,

I

LDO2

= 1mA to 100 mA

20

V

D

I

LDO1

= 100mA

100

150

mV

Current Limit

I

LIM

200

mA

Power Supply

Rejection Ratio

PSRR

LDO1

2.5V < V

LDO1

< 3V, f < 1kHz, C

BYP

= 22nF, I

LDO1

= 50mA,

V

IN

= 3.7V with 0.5V

P-P

ripple

50

dB

PSRR

LDO2

f < 1kHz, C

BYP

= 22nF, I

LDO2

= 50mA,

V

IN

= 3.7V with 0.5V

P-P

ripple

60

Output Voltage Noise

e

n-LDO1

LDO1, 10Hz < f < 100kHz, C

BYP

= 22nF, C

LDO

= 1μF,

I

LDO1

= 50 mA, V

IN

= 3.7V, 2.5V < V

LDO1

< 3V

100

μV

RMS

e

n-LDO2

LDO2, 10Hz < f < 100kHz, C

BYP

= 22nF, C

LDO

= 1μF,

I

LDO2

= 50 mA, V

IN

= 3.7V

50

Minimum Output Capacitor

C

LDO(MIN)

1μF

Digital I/O Electrical Specifications (FLEN, SWIF)

Input High Threshold

V

IH

V

IN

= 5.5V

1.6

V

Input Low Threshold

V

IL

V

IN

= 3.0V

0.4

V

Input High Current

I

IH

V

IN

= 5.5V

-1

+1

μA

Input Low Current

I

IL

V

IN

= 5.5V

-1

+1

μA

SemWire Bit Rate

f

SWIF

10

75

kbit/s

t

EN

1ms

t

DIS

10

ms

D

DL

5

bit

Notes:

(1)

ΔV

F

is the voltage difference between any two LEDs.

(2)

Once tripped, flash output will remain disabled until FLEN pin is cycled or reset via serial interface.

(3)

Current matching equals ± [I

BL(MAX)

- I

BL(MIN

] / [I

BL(MAX)

+ I

BL(MIN)

].

(4)

Test voltage is V

OUT

= 4.0V — a relatively extreme LED voltage — to force a transition during test. Typically V

OUT

= 3.2V for white LEDs.

(5)

Dropout is defined as (V

IN

- V

LDO1

) when V

LDO1

drops 100mV from nominal. Dropout does not apply to LDO2 since it has a maximum output voltage

of 1.8V.

(6)

The SemWire start-up time is the minimum period that the SWIF pin must be held high to enable the part before commencing

communication.

(7)

The SemWire disable time is the minimum period that the SWIF pin must be pulled low to shut the part down.

(8)

The SemWire data latch delay is the maximum duration after communication has ended before the register is updated.