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HT9032C 数据表(PDF) 6 Page - Holtek Semiconductor Inc |
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HT9032C 数据表(HTML) 6 Page - Holtek Semiconductor Inc |
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6 / 14 page ![]() Application Circuits Application circuit 1 Application circuit 2 HT9032C/HT9032D Rev. 1.40 6 September 30, 2002 Normally, the PDWN pin and the RTIME pin control the operation mode of the HT9032. When both pins are HIGH, the HT9032 is set at the power down mode, con- suming less than 1 mA of supply current. When a valid power ring arrives, the RTIME pin will be driven below VT- and the portions of the part involved in the ring signal analysis are enabled. This is partial power up mode, consuming approximately 1.9mA typically. Once the PDWN pin is below VT-, the part will be fully powered up, and ready to receive FSK. During this mode, the device current will increase to approximately 3.2mA (typ). The state of the RTIME pin is now a ²don¢t care² as far as the part is concerned. After the FSK message has been re- ceived, the PDWN pin can be allowed to return to VDD and the part will return to the power down mode. H T 1 0 5 0 ~ ~ T I P V D D X 2 P D W N V S S R I N G X 1 D O U T H T 9 0 3 2 D 3 . 5 8 M H z 1 0 M W 3 0 p . 3 0 p . 1 5 k W 1 8 k W 2 0 0 k W 0 . 0 1 m . 4 7 0 k W 0 . 0 1 m . 2 0 0 k W 0 . 2 m . T I P R I N G 0 . 2 m . 0 . 1 m . 9 V V D D M C U H T 1 0 5 0 ~ ~ T I P V D D R T I M E R D E T 1 X 2 P D W N V S S R I N G C D E T R D E T X 1 R D E T 2 D O U T C D O U T H T 9 0 3 2 C 2 0 k W 2 0 k W 3 . 5 8 M H z 1 0 M W 3 0 p . 3 0 p . V D D 2 7 0 k W 0 . 2 m . 1 5 k W 1 8 k W 2 0 0 k W 0 . 0 1 m . 4 7 0 k W 0 . 0 1 m . 2 0 0 k W 0 . 2 m . T I P R I N G 0 . 2 m . 0 . 1 m . 9 V V D D M C U |
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