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MAX9423 数据表(PDF) 3 Page - Maxim Integrated Products |
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MAX9423 数据表(HTML) 3 Page - Maxim Integrated Products |
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3 / 13 page ![]() Quad Differential LVECL-to-LVPECL Translators _______________________________________________________________________________________ 3 DC ELECTRICAL CHARACTERISTICS (continued) (VEE = -2.0V to -3.6V, VCC = 2.375V to 3.6V, GND = 0, MAX9420/MAX9422 outputs terminated with 50 Ω ±1% to VCC - 2.0V. Typical val- ues are at VEE = -3.3V, VCC = 3.3V, TA = +25°C, VIHD = -0.9V, VILD = -1.7V, unless otherwise noted.) (Notes 1, 2, and 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Negative Supply Current IEE OUT_, OUT_ open MAX9421/MAX9422/ MAX9423 710 mA MAX9421/MAX9423 153 -180 Positive Supply Current ICC OUT_, OUT_ open MAX9420/MAX9422 87 105 mA AC ELECTRICAL CHARACTERISTICS (VEE = -2.0V to -3.6V, VCC = 2.375V to 3.6V, GND = 0, outputs terminated with 50 Ω ±1% to VCC - 2.0V. For SEL = high, CLK = high or low, fIN = 2.0GHz. For SEL = low, FIN = 1.5GHz, CLK = 3.0GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.4V to 0, VILD = VEE to -0.2V, VIHD - VILD = 0.2V to the smaller of 3.0V or |VEE|. Typical values are at VEE = -3.3V, VCC = 3.3V, GND = 0, TA = +25°C, VIHD = -0.9V, VILD = -1.7V, unless otherwise noted.) (Note 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IN-to-OUT Differential tPLH1, tPHL1 SEL = high, Figure 3 250 336 450 ps CLK-to-OUT Differential tPLH2, tPHL2 SEL = low, Figure 4 350 506 575 ps IN-to-OUT Channel-to-Channel Skew (Note 5) tSKD1 SEL = high 17 60 ps CLK-to-OUT Channel-to- Channel Skew (Note 5) tSKD2 SEL = low 17 55 ps Maximum Clock Frequency fCLK(MAX) VOH - VOL ≥ 500mV, SEL = low 3.0 GHz Maximum Data Frequency fIN(MAX) VOH - VOL ≥ 400mV, SEL = high 2 GHz SEL = low, fCLK = 3.0GHz, fIN = 1.5GHz 0.65 1.0 ps(RMS) Added Random Jitter (Note 6) tRJ SEL = high, fIN = 2GHz 0.53 1.0 ps(RMS) SEL = low, fCLK = 3.0GHz, IN_ = 3.0Gbps, 2 23 - 1 PRBS pattern 28 45 Added Deterministic Jitter (Note 6) tDJ SEL = high, IN_ = 3.0Gbps 2 23 - 1 PRBS pattern 23 45 ps(P-P) IN-to-CLK Setup Time tS Figure 4 80 ps CLK-to-IN Hold Time tH Figure 4 80 ps Output Rise Time tR Figure 3 90 120 ps |
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