Quad Differential LVECL-to-LVPECL Translators

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5

Pin Description

PIN

NAME

FUNCTION

1, 8

capacitors as close to the device as possible with the smaller value capacitor closest to the device.

2

SEL

Noninverting Differential Select Input. Setting SEL = high and SEL = low (differential high) enables all four

channels to operate asynchronously. Setting SEL = low and SEL = high (differential low) enables all four

channels to operate in synchronous mode.

3

SEL

Inverting Differential Select Input

4

CLK

Inverting Differential Clock Input. A rising edge on CLK (and falling on CLK) transfers data from the inputs to

the outputs when SEL = differential low.

5

CLK

Noninverting Differential Clock Input

6EN

Noninverting Differential Output Enable Input. Setting EN = high and EN = low (differential high) enables the

outputs. Setting EN = low and EN = high (differential low) drives the output low.

7

EN

Inverting Differential Output Enable Input

9

IN3

Noninverting Differential Input 3

10

IN3

Inverting Differential Input 3

11, 17,

24, 30

capacitors as close to the device as possible with the smaller value capacitor closest to the device.

12

OUT3

Inverting Differential Output 3

13

OUT3

Noninverting Differential Output 3

14, 20,

21, 27

GND

Ground

15

IN2

Noninverting Differential Input 2

16

IN2

Inverting Differential Input 2

18

OUT2

Inverting Differential Output 2

19

OUT2

Noninverting Differential Output 2

22

OUT1

Noninverting Differential Output 1

23

OUT1

Inverting Differential Output 1

25

IN1

Inverting Differential Input 1

26

IN1

Noninverting Differential Input 1

28

OUT0

Noninverting Differential Output 0

29

OUT0

Inverting Differential Output 0

31

IN0

Inverting Differential Input 0

32

IN0

Noninverting Differential Input 0

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EP