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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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STVM100 数据表(PDF) 16 Page - STMicroelectronics |
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STVM100 数据表(HTML) 16 Page - STMicroelectronics |
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16 / 27 page  DC and AC parameters STVM100 16/27 Figure 9. Bus timing requirements sequence Table 8. AC characteristics Sym Description Test Condition(1) 1. Valid for ambient operating temperature: TA = –40 to 85°C; VDD = 3.0V to 3.6V; AVDD = 10V; OUT = 1/2AVDD; RSET = 24.9kΩ (except where noted, see Figure 9). Min Typ Max Unit fSCL SCL clock frequency 0 400 kHz tLOW Clock low period 1.3 µs tHIGH Clock high period 0.6 µs tSU:DAT Data setup time 100 ns tHD:DAT Data hold time 0 900 ns tR SDA and SCL rise time Dependent on load (see Table 6 on page 14) 20 + 0.1Cb 300 ns tF SDA and SCL fall time 300 ns tBUF Bus free time before new transmission can start 1.3 µs tDSP I2C spike rejection filter pulse width 050 ns tSU:STA Repeated start condition setup time 0.6 µs tHD:STA Repeated start condition hold time 0.6 µs tSU:STO Stop condition setup time 0.6 µs tW WRITE cycle time 100 ms AI00589 SDA P tSU:ST tSU:STA tHD:STA SR SCL tSU:DAT tF tHD:DAT tR tHIGH tLOW tHD:STA tBUF S P |
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