PI7C8152AMA datasheet(77/90 Pages) PERICOM

77 / 90 page

PI7C8152A & PI7C8152B

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 77 of 90

October 16, 2003 – Revision 1.11

Bit

Function

Type

Description

Memory Write

Disconnect

Control

R/W

Controls when the bridge (as a target) disconnects memory write

transactions.

0: memory write disconnects at 4KB aligned address boundary

1: memory write disconnects at cache line aligned address boundary

Reset to 0

3:2

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0.

Secondary Bus

Prefetch Disable

R/W

Controls the bridge’s ability to prefetch during upstream memory

read transactions

0: PI7C8152x prefetches and does not forward byte enable bits

during upstream memory read transactions.

1: PI7C8152x requests only 1 DWORD from the target and forwards

read byte enable bits during upstream memory reads.

Reset to 0

7:5

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0

Chip Reset

R/WR

Controls the chip and secondary bus reset.

0: PI7C8152x is ready for operation

1: Causes PI7C8152x to perform a chip reset. Data buffers,

configuration registers, and both primary and secondary are reset to

their initial states. PI7C8152x clears this bit once chip reset is

complete. PI7C8152x can then be reconfigured.

Test Mode 1

R/W

Controls the ability to test PI7C8152x’s behavior

0: minimum of 8 free space in data FIFO to accept memory burst

writes

1: minimum of 1 free space in data FIFO to accept memory burst

writes

Reset to 0

11:10

Test Mode 2

R/W

Controls the ability to test PI7C8152x’s behavior

00: enable out of order transactions between all 4 DTR requests

01: accept 3 DTR requests at a time and they may be out of order

10: only the 2 DTR requests at the top of the 2 FIFO’s may be out of

order

11: no out of order transactions supported between DTR requests

Reset to 00

Test Mode 3

R/W

Controls the ability to test PI7C8152x’s behavior

0: 4 memory write transactions can be accepted at a time

1: 2 memory write transactions can be accepted at a time

Reset to 0

15:13

Reserved

R/O

Reserved. Returns 000 when read. Reset to 000.

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