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PCAL6408A

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Product data sheet

Rev. 3 — 18 September 2013

20 of 49

NXP Semiconductors

PCAL6408A

Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander

Reducing the current drive capability may be desirable to reduce system noise. When the

output switches (transitions from H/L), there is a peak current that is a function of the

output drive selection. This peak current runs through VDD and VSS package inductance

and creates noise (some radiated, but more critically Simultaneous Switching Noise

(SSN)). In other words, switching many outputs at the same time creates ground and

supply noise. The output drive strength control through the Output Drive Strength

registers allows the user to mitigate SSN issues without the need of additional external

components.

9.3 Power-on reset requirements

In the event of a glitch or data corruption, PCAL6408A can be reset to its default

conditions by using the power-on reset feature. Power-on reset requires that the device

go through a power cycle to be completely reset. This reset also happens when the device

is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 19 and Figure 20.

Table 19 specifies the performance of the power-on reset feature for PCAL6408A for both

types of power-on reset.

Fig 19. VDD is lowered below 0.2 V or 0 V and then ramped up to VDD

Fig 20. VDD is lowered below the POR threshold, then ramped back up to VDD

002aag960

VDD(P)

time

ramp-up

ramp-down

(dV/dt)r

(dV/dt)f

re-ramp-up

(dV/dt)r

time to re-ramp

when VDD(P) drops

below 0.2 V or to VSS

td(rst)

002aag961

VDD(P)

time

ramp-down

(dV/dt)f

ramp-up

(dV/dt)r

time to re-ramp

when VDD(P) drops

to VPOR(min) − 50 mV

td(rst)

VI drops below POR levels

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