Quad, Low-Voltage, SPST Analog Switches

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9

GND

NC or

NO

V-

V-

V+

IN

OFF

ON

OFF

Q = (

COM

IN DEPENDS ON SWITCH CONFIGURATION;

INPUT POLARITY DETERMINED BY SENSE OF SWITCH.

OFF

ON

OFF

IN

V+

IN

MAX4521

MAX4522

MAX4523

Figure 3. Charge Injection

50%

+3V

0

0

LOGIC

INPUT

SWITCH

OUTPUT 2

0

LOGIC

INPUT

V-

V-

GND

COM2

IN1, 2

COM1

V+

V+

Ω

NO

NC

SWITCH

OUTPUT 1

MAX4523

Figure 1. Switching Time

Figure 2. Break-Before-Make Interval (MAX4523 only)

Test Circuits/Timing Diagrams

tr < 20ns

tf < 20ns

50%

0

LOGIC

INPUT

V-

V-

300

Ω

NO

or NC

GND

(

)

SWITCH

INPUT

IN, EN

+3V

0

COM

SWITCH

OUTPUT

SWITCH

OUTPUT

LOGIC

INPUT

LOGIC INPUT WAVEFORMS INVERTED FOR EN AND SWITCHES

THAT HAVE THE OPPOSITE LOGIC SENSE.

35pF

V+

V+

0

MAX4521

MAX4522

MAX4523