ST7263BHX datasheet(90/145 Pages) STMICROELECTRONICS

部件名	ST7263BHX

功能描述	Low speed USB 8-bit MCU family with up to 32K Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI & I짼C

PDF	145 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

90 / 145 page

ST7263BDx ST7263BHx ST7263BKx ST7263BE

90/145

sion. The resetting of the BUSY bit can then be

handled in a similar manner as the BERR flag

being set.

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set by hardware

with an interrupt if the ITE bit is set. To resume,

set the START or STOP bit.

The AF bit is cleared by reading the I2CSR2 reg-

ister. However, if read before the completion of

the transmission, the AF flag will be set again,

thus possibly generating a new interrupt. Soft-

ware must ensure either that the SCL line is back

at 0 before reading the SR2 register, or be able

to correctly handle a second interrupt during the

9th pulse of a transmitted byte.

– ARLO: Detection of an arbitration lost condition.

In this case the ARLO bit is set by hardware (with

an interrupt if the ITE bit is set and the interface

goes automatically back to slave mode (the M/SL

bit is cleared).

Note: In all these cases, the SCL line is not held

low; however, the SDA line can remain low if the

last bits transmitted are all 0. While AF=1, the SCL

line may be held low due to SB or BTF flags that

are set at the same time. It is then necessary to re-

lease both lines by software.

ST7263BHX 数据表(PDF) 90 Page - STMicroelectronics