Functional description

STDS75

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3.3

Serial interface

Writing to and reading from the STDS75 registers is accomplished via the two-wire serial

interface protocol which requires that one device on the bus initiates and controls all READ

and WRITE operations. This device is called the “master” device. The master device also

generates the SCL signal which provides the clock signal for all other devices on the bus.

These other devices on the bus are called “slave” devices. The STDS75 is a slave device

(see Table 10). Both the master and slave devices can send and receive data on the bus.

During operations, one data bit is transmitted per clock cycle. All operations follow a

repeating, nine-clock-cycle pattern that consists of eight bits (one byte) of transmitted data

followed by an acknowledge (ACK) or not acknowledge (NACK) from the receiving device.

Note:

There are no unused clock cycles during any operation, so there must not be any breaks in

the data stream and ACKs/NACKs during data transfers. Conversely, having too few clock

cycles can lead to incorrect operation if an inadvertent 8-bit READ from a 16-bit register

occurs.

3.4

2-wire bus characteristics

The bus is intended for communication between different ICs. It consists of two lines: a bi-

directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be

connected to a positive supply voltage via a pull-up resistor.

●

The following protocol has been defined:

●

Data transfer may be initiated only when the bus is not busy.

●

During data transfer, the data line must remain stable whenever the clock line is High.

●

Changes in the data line, while the clock line is High, will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined (see Figure 6 on page 21):

3.4.1

Bus not busy

Both data and clock lines remain High.

3.4.2

Start data transfer

A change in the state of the data line, from high to Low, while the clock is High, defines the

START condition.

3.4.3

Stop data transfer

A change in the state of the data line, from Low to High, while the clock is High, defines the

STOP condition.

Table 10.

STDS75 serial bus slave addresses

MSB

LSB

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

1

0

0

1

A2

A1

A0

R/W