数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

GL9701 数据表(PDF) 39 Page - GENESYS LOGIC

部件名 GL9701
功能描述  PCI ExpressTM to PCI Bridge
PDF  75 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  GENESYS [GENESYS LOGIC]
网页  http://www.genesyslogic.com
标志 GENESYS - GENESYS LOGIC

GL9701 数据表(HTML) 39 Page - GENESYS LOGIC

Back Button GL9701 Datasheet HTML 35Page - GENESYS LOGIC GL9701 Datasheet HTML 36Page - GENESYS LOGIC GL9701 Datasheet HTML 37Page - GENESYS LOGIC GL9701 Datasheet HTML 38Page - GENESYS LOGIC GL9701 Datasheet HTML 39Page - GENESYS LOGIC GL9701 Datasheet HTML 40Page - GENESYS LOGIC GL9701 Datasheet HTML 41Page - GENESYS LOGIC GL9701 Datasheet HTML 42Page - GENESYS LOGIC GL9701 Datasheet HTML 43Page - GENESYS LOGIC Next Button
Zoom Inzoom in Zoom Outzoom out
 39 / 75 page
background image
GL9701 PCI Express
TM to PCI Bridge
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 39
6.12 Offset 18h: Primary Bus Number Register
Bits
Type
Default
Description
7:0
RW
00h
Primary Bus Number: Used to record the Bus Number of the
logical PCI bus segment to which the primary interface of the
bridge is connected. Configuration software is required to program
the value into this register..
6.13 Offset 19h: Secondary Bus Number Register
Bits
Type
Default
Description
7:0
RW
00h
Secondary Bus Number: Used to record the Bus Number of the
PCI bus segment to which the secondary interface of the bridge is
connected. Configuration software programs the value in this
register.
6.14 Offset 1ah: Subordinate Bus Number Register
Bits
Type
Default
Description
7:0
RW
00h
Subordinate Bus Number: Used to record the Bus Number of the
highest numbered PCI bus segment which is downstream of (or
subordinate to) the bridge. Configuration software programs the
value in this register.
6.15 Offset 1bh: Secondary Latency Timer Register
Bits
Type
Default
Description
7:0
RW
00h
Secondary Latency Timer: This register specifies, in units of PCI
bus clocks, the value of the Latency Timer for the secondary
interface GL9701.
6.16 Offset 1ch: IO Base and IO Limit Register
Bits
Type
Default
Description
3:0
RO
0h
I/O Base Addressing Capability: Each of these bits is hard-wired



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com