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TDA7421N

Figure 5. Phase Comparator

5.5 Acknowledge

Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data. During the 9th

clock cycle the receiver will pull the SDA line to LOW level to indicate it has received the eight bits of data correctly.

5.6 Data transfer

During data transfer the TDA7421N samples the SDA line on the leading edge of the SCL clock, Therefore, for

proper device operation the SDA line must be stable during the SCL LOW to HIGH transition.

5.7 Device Addressing

To start the communication between two devices, the bus master must initiate a start instruction sequence, fol-

lowed by an eight bit word corresponding to the address of the device it is addressing. The most significant 6

bits of the slave address identify the device type.

The TDA7421N device code is fixed as "110001".

The next significant bit is used either to address the tuner section (1) or the PLL section (0) of the chip.

Following a START condition the master sends slave address word; the TDA7421N will "acknowledge" after this

first transmission and wait for a second word (the word address field).This 8 bit address field provides an access

to any of the 8 internal addresses. Upon receipt of the word address the TDA7421N slave device will respond

with an "acknowledge".

At this time, all the following words transmits to the TDA7421N will be considered as data.The internal address

will be automatically incremented. After each word receipt the TDA7421N will answer with an "acknowledge".

The interface protocol comprises:

– a subaddress byte

– a sequence of data (N-bytes + acknowledge)

– a stop condition (P)

– a start condition (S)

– a chip address byte