ADS5474IPFPR datasheet(7/38 Pages) TI

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TIMING INFORMATION

CLK

OVR

[13:0],

N+1

N+5

CLKL

DRY

DATA

CLKH

D[13:0], OVR

CLK

N+2

N+3

N+4

DRY

(1)

N+1

N–1

Sample

N–1

Latency = 3.5 Clock Cycles

TIMING CHARACTERISTICS

(1)

ADS5474

SLAS525 – JULY 2007

(1)

Polarity of DRY is undetermined. For further information, see the Digital Outputs section.

Figure 1. Timing Diagram

Typical values at TA = +25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = +85°C,

sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential

clock, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperture delay

200

Aperture jitter, rms

Internal jitter of the ADC

103

Latency

3.5

cycles

tCLK

Clock period

2.5

tCLKH

Clock pulse duration, high

tCLKL

Clock pulse duration, low

tDRY

CLK to DRY delay(2)

Zero crossing, 10-pF parasitic loading to GND on each

1000

1400

1800

output pin

tDATA

CLK to DATA/OVR delay(2)

Zero crossing, 10-pF parasitic loading to GND on each

800

1400

2000

output pin

tSKEW

DATA to DRY skew

tDATA – tDRY, 10-pF parasitic loading to GND on each output

–500

500

tRISE

DRY/DATA/OVR rise time

10-pF parasitic loading to GND on each output pin

500

tFALL

DRY/DATA/OVR fall time

10-pF parasitic loading to GND on each output pin

500

(1)

Timing parameters are assured by design or characterization, but not production tested.

(2)

DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the overall propagation

delay.

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