R2021

R

R

FAST ETHERNET RISC PROCESSOR

Specifications subject to change without notice, contact your sales representatives for the most update information.

Page 2 of 4

REV 1.0 Sep. 20 2006

1.

Features

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CPU Core

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RDC’s proprietary RISC architecture

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Five-stage pipeline

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Operation frequency: 125 MHz

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Supports an 8K-byte Uniform cache

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Supports CPU ID

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Supports 40 PIO pins

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Bus Interface

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Supports non-multiplexed address bus A[21:0]

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With 8-bit or 16-bit Boot ROM bus size

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8-bit or 16-bit external bus dynamic access

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Supports an independent data/address bus for

external I/O device

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PCMCIA Bus Interface

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Supports a glueless and simplified 16-bit PCMCIA

bus interface

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ROM/RAM/SDRAM Controller and Addressing

Space

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Supports 16-bit data bus [15:0]

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16M-byte memory address space Address[23:0]

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SDRAM control Interface

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64K-byte I/O space

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Compatible UART Channels

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Supports two compatible UART serial channels

with 16-byte FIFO and hardware flow-control

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Two Independent DMA Channels

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Fast Ethernet MAC Ports

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2-Port Fast Ethernet MAC with MII interface

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The MAC packet buffer is cacheble with snooping

function

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Interrupt Controller

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The Interrupt controller with five maskable

external interrupts and one non-maskable external

interrupt

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Programmable Chip-select Logic

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Programmable chip-select logic for Memory or

I/O bus cycle decoder

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Programmable wait-state generator

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Counter/Timers

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Three independent 16-bit timers and one

independent programmable watchdog timer

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Operating Voltage Range

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Core voltage: 2.5V ± 5%

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I/O voltage: 3.3V ± 10%

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Package Type

128-pin PQFP