TDA7303

I2C bus interface

13/21

3

Data transmission from microprocessor to the TDA7303 and viceversa takes place thru the

positive supply voltage must be connected).

3.1

Data validity

As shown in Figure 20, the data on the SDA line must be stable during the high period of the

clock. The HIGH and LOW state of the data line can only change when the clock signal on

the SCL line is LOW.

3.2

Start and stop conditions

As shown in Figure 21 a start condition is a HIGH to LOW transition of the SDA line while

SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is

HIGH.

3.3

Byte format

Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by

an acknowledge bit. The MSB is transferred first.

3.4

Acknowledge

The master (

µP) puts a resistive HIGH level on the SDA line during the acknowledge clock

pulse (see Figure 22). The peripheral (audioprocessor) that acknowledges has to pull-down

(LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW

during this clock pulse.

The audioprocessor which has been addressed has to generate an acknowledge after the

reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth

clock pulse time. In this case the master transmitter can generate the STOP information in

order to abort the transfer.

3.5

Transmission without acknowledge

Avoiding to detect the acknowledge of the audioprocessor, the

µP can use a simplier

transmission: simply it waits one clock without checking the slave acknowledging, and sends

the new data.

This approach of course is less protected from misworking and decreases the noise

immunity.