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ELANSC310 数据表(PDF) 95 Page - Advanced Micro Devices |
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ELANSC310 数据表(HTML) 95 Page - Advanced Micro Devices |
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95 / 119 page ![]() Élan™SC310 Microcontroller Data Sheet 95 PREL IMINARY For more information about DRAM bank miss read wait states, see the DRAM Bank Miss Wait State Select Logic table in Chapter 4 of the ÉlanTMSC310 Microcontroller Programmer’s Reference Manual, order #20665. t44b CAS hold from RAS Low 375 ns 4 105 ns 5 120 ns t47 D15–D0 hold from CAS High (read) N/A 0 ns Table 48. DRAM Bank/Page Miss Read Cycles (See Figure 38) (Continued) Symbol Parameter Description Wait State Min Max Unit t41a RAS t36 t40 t38 t30 t31 t34 t44a t39 t5b t47 MA10–MA0 CAS MWE D15–D0 Figure 38. DRAM First Cycle and Bank/Page Miss (Read Cycles) t32 First Cycle Bank/Page Miss t33 t5a t28a t28b t41b t39 t29a t44b |
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