GS7103PP-R datasheet(11/15 Pages) GSTEK

11 / 15 page

3A Ultra Low Dropout Linear Regulator

GS7103

Green Solution Technology Co.,LTD.

Rev.:1.6

JUN-16

Feedback Network

Figure 3 shows the feedback network. The

suggested design procedure is to choose

R2=10KΩ and then calculate R1 using the

following formula: R1=(VOUT / VREF -1)*R2.

Figure 3 Feedback Network

COPTION can improve transient response, and

recommend value as follow:

VOUT

COPTION

0.8V ~ 1.6V

0 ~ 10 KΩ

470pF~1nF

1.6V ~ 2.4V

10 KΩ ~ 20 KΩ

100pF~500pF

2.4V ~ 3.6V

20 KΩ ~ 30 KΩ

20pF~300pF

Table 2 R1 vs. COPTION

Input Capacitor selection

Bypass VIN to ground with a 10uF or greater

capacitor. Bypass VDD to ground with a 1uF

capacitor for normal operation in most appli-

cations. Ceramic, tantalum or aluminum elec-

trolytic capacitors may be selected for input

capacitor. However ceramic capacitors are

recommended due to their significant cost and

space savings. Place the capacitors physically as

close as possible to the device with wide and

direct PCB traces.

Power Dissipation and Layout Considerations

Although internal thermal limiting function is

integrated in GS7103, continuously keeping the

junction near the thermal shutdown temperature

may possibly affect device reliability. For

continuous operation, it is highly recommended to

keep the junction temperature below the

maximum operation junction temperature 125°C

for maximum reliability.

The power dissipation definition in device is:

PD = (VIN − VOUT) x IOUT + VDD x IQ

The

maximum

power

dissipation

can

calculated as:

PD(MAX) = ( TJ(MAX) − TA ) / θJA

Where TJ(MAX) is the maximum operation junction

temperature

125°C,

the

ambient

temperature and the θJA is the junction to ambient

thermal resistance.

The thermal resistance θJA for PSOP-8 package

is 75°C/W on the standard JEDEC 51-7 (4 layers,

2S2P) thermal test board. The copper thickness

is 2oz. The maximum power dissipation at TA =

25°C can be calculated by following formula:

PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.33W

(SOP-8 Exposed Pad on the minimum layout)

The thermal resistance θJA for TDFN10-3x3

package is 60°C/W on the standard JEDEC 51-7

(4 layers, 2S2P) thermal test board. The

maximum power dissipation at TA = 25°C can be

calculated by following formula:

PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.67W

The thermal resistance θJA of PSOP-8 is

determined by the package design and the PCB

design. Copper plane under the exposed pad is

an effective heat sink and is useful for improving

thermal conductivity. As shown in Figure 3, the

amount of copper area to which the PSOP-8 is

mounted affects thermal performance. When

mounted to the standard PSOP-8 pad (Figure

4.a), θJA is 75°C/W. Adding copper area of pad

under the PSOP-8 Figure 4.b) reduces the θJA to

54°C/W. Even further, increasing the copper area

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