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PN8370SSC-R1 数据表(PDF) 7 Page - Wuxi Chipown Micro-electronics limited |
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PN8370SSC-R1 数据表(HTML) 7 Page - Wuxi Chipown Micro-electronics limited |
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7 / 10 page ![]() PN8370 13/F, Building C, Wangzhuang Technology Innovation Center, Longshan Road,New District, Wuxi Tel: +86(510)85217718 http://www.chipown.com.cn Rev.A.1507 7 / 10 AUX S CV REF N N R R R V Vo × + × = ) 2 2 1 ( _ ( 3) S N means Secondary winding, AUX N means Auxiliary winding The PN8370 operates in PFM_QR mode during full load mode, since the peak current (Ipeak) of MOSFET is constant, the chip frequency decreases while the output current decreases. When the switching frequency approaches to 25kHz, the PN8370 enters PWM_QR mode , the chip frequency decreases slowly while the output current decreases, the Ipeak decreases while the output current decreases. Therefore the PN8370 can avoid audible noise, while achieving high efficiency at 25% load conditions. When Vcs decreases to 170mV, the PN8370 enters Standby mode. In this mode, Ipeak keeps around constant, the chip oscillator frequency decreases while the output current decreases. Figure 2 illustrates the relations of the switching frequency, Ipeak and Loading for PN8370. Figure 2 The Switching Frequency, Vipeak VS. LOAD 4. Current Sensing and Leading Edge Blanking Cycle-by-Cycle current limiting is offered in PN8370. The switch current is detected by a sense resistor at CS pin. The CC set-point and maximum output power can be externally adjusted by external current sense resistor at CS pin. An internal leading edge blanking circuit chops off the sensed voltage spike at initial power MOSFET on-state so that the external RC filtering on sense input is no longer needed. 5. Programmable Cable Drop Compensation In PN8370, an offset voltage is generated at FB pin by an internal current flowing into the divider resister, as shown in Figure 3. The Cable Drop Compensation block compensates the voltage drop across the cable. As the load current decreases from full load to no load, the voltage drop across the cable decreases. It can be programmed by adjusting the external resistor R2 or R1 at FB pin. The maximum compensation is V R R I V V cable O cable 5 . 2 ) 1 // 2 ( × = ( 4) Because of the influence of the chip’s sampling position and devices of the system, the actual maximum compensation is less than theoretical value. |
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