Advanced CMOS TTL Input – 54ACT05

Hex Inverter Gate with Open-Drain Outputs in bare die form

Rev 1.0

10/05/19

Inputs directly accept TTL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Die Size (Unsawn)

1100 x 1260

43 x 50

µm

mils

Minimum Bond Pad Size

108 x 108

4.25 x 4.25

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si

Outputs directly interface CMOS, NMOS and TTL

Outputs Source/Sink 24 mA

Low Input Current: 1µA

Functionally compatible with bipolar 54LS05

Lower power alternative to bipolar logic

Full Military Temperature Range

Features:

Ordering Information

The 54ACT05 hex inverter gate is fabricated on a 1.5µm

advanced 5V CMOS process combining high speed

LSTTL performance with CMOS low power. The device

contains six independent inverters with open-drain

outputs and perform the Boolean function Y = Ᾱ.

Device outputs can connect with other open-drain

outputs to form active LOW wired-OR or active HIGH

wired-AND logic functions. Open-drain outputs need

pull-up resistors to perform correctly*. Inputs are directly

compatible with both standard TTL and CMOS outputs.  

 

Description

Die Dimensions in µm (mils)

The following part suffixes apply:

No suffix - MIL-STD-883 /2010B Visual Inspection

“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification

1100 (43)

Default – Die in Waffle Pack (400 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 350µm(14 Mils) – On request

Assembled into Ceramic Package – On request

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